DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 6/30/2026 is acknowledged.
Claim Objections
Claim 1 and 21 are objected to because of the following informalities: the claim appears to have a typographical error "a gate structure, comprising;". For the purpose of examination, the examiner will interpret the above limitation as "a gate structure, comprising:". Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 21-24 and 26-30 are rejected under 35 U.S.C. 103 as being unpatentable over Kavalieros et al.US 2020/0312978 in view of Jangjian et al. US 2015/0054029.
Re claim 1, Kavalieros teaches a semiconductor device (fig4B), comprising:
a substrate (410, fig4B, [69]);
a fin structure (413, fig4B, [73]) disposed on the substrate;
a gate structure (420 and 460, fig4A and 4B, [69, 74]).
Kavalieros does not explicitly show a gate structure, comprising: a high-k gate oxide layer disposed on the fin structure, a first diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer disposed on the first diffusion barrier layer;
Jangjian teaches a gate structure (220, fig8, [18]), comprising: a high-k gate oxide layer (224, fig8, [39]) disposed on the fin structure (channel between 212, fig8, [16]), a first diffusion barrier layer (250 as TiN, fig8, [39]) disposed on the high-k gate oxide layer (224, fig8, [39]), and a metal layer (246, fig8, [34]) disposed on the first diffusion barrier layer;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kavalieros and Jangjian to replace Kavalieros 420 with Jangjian 222-250 and Kavalieros 460 with Jangjian 242-246. The motivation to do so is to reduce leakage current and improve device performance (Jangjian, [37, 39]).
Kavalieros in view of Jangjian teaches a gate spacer (Kavalieros, 430a/b, fig4B, [71]) disposed on the first diffusion barrier layer (Jangjian 250 added as top part of Kavalieros 420 in fig4B); and
a source/drain (S/D) region (Kavalieros, 417/419, fig4B, [74]) disposed on the fin structure,
wherein a sidewall of the S/D region (Kavalieros, 417/419, fig4B, [74]) is in contact with a sidewall of the high-k gate oxide layer (Kavalieros 420 replaced by Jangjian 222-250 and 224 as high-K, fig4B).
Re claim 2, Kavalieros in view of Jangjian teaches the semiconductor device of claim 1, wherein the gate spacer (Kavalieros, 430a/b, fig4B, [71]) is disposed on a top surface of the first diffusion barrier layer (Jangjian 250 added as top part of Kavalieros 420 in fig4B).
Re claim 3, Kavalieros in view of Jangjian teaches the semiconductor device of claim 1, wherein the gate spacer (Kavalieros, 430a/b, fig4B, [71]) is disposed on a top surface of the high-k gate oxide layer (Kavalieros 420 replaced by Jangjian 222-250 and 224 as high-K, fig4B).
Re claim 4, Kavalieros in view of Jangjian teaches the semiconductor device of claim 1, wherein the gate spacer (Kavalieros, 430a/b, fig4B, [71]) is disposed on a first top surface portion of the first diffusion barrier layer (Jangjian 250 added as top part of Kavalieros 420 in fig4B and part of Jangjian 250 in contact with Kavalieros 430a/b as a first top surface portion), and wherein the metal layer (Kavalieros 460 replaced by Jangjian 242-246 and 246 as Al, fig4B) is disposed on a second top surface portion of the first diffusion barrier layer (part of Jangjian 250 directly under Kavalieros 460 as a second top surface portion, fig4B).
Re claim 5, Kavalieros in view of Jangjian teaches the semiconductor device of claim 1, wherein a horizontal portion of the gate spacer (Kavalieros, lower part of 430a/b in contact with 420, fig4B) is disposed on the first diffusion barrier layer, and wherein a vertical portion of the gate spacer (Kavalieros, upper part of 430a/b, fig4B) is disposed on the metal layer (Kavalieros 460 replaced by Jangjian 242-246 and 246 as Al, fig4B).
Re claim 6, Kavalieros in view of Jangjian teaches the semiconductor device of claim 1, wherein a horizontal portion of the gate spacer (Kavalieros, lower part of 430a/b in contact with 420, fig4B) is disposed on the high-k gate oxide layer (Kavalieros 420 replaced by Jangjian 222-250 and 224 as high-K, fig4B), and wherein a vertical portion of the gate spacer (Kavalieros, upper part of 430a/b, fig4B) is disposed on the metal layer (Kavalieros 460 replaced by Jangjian 242-246 and 246 as Al, fig4B).
Re claim 7, Kavalieros in view of Jangjian teaches the semiconductor device of claim 1, further comprising a second diffusion barrier layer (Jangjian, 242, fig8, [26]) disposed on the first diffusion barrier layer (Jangjian, 250, fig8, [39]), wherein: a horizontal portion of the gate spacer (Kavalieros, lower part of 430a/b in contact with 420, fig4B) is disposed on the first diffusion barrier layer (Jangjian 250 added as top part of Kavalieros 420 in fig4B); and a vertical portion of the gate spacer (Kavalieros, upper part of 430a/b, fig4B) is disposed on the second diffusion barrier layer (Kavalieros 460 replaced by Jangjian 242-246 with 242 as second diffusion barrier layer, fig4B).
Re claim 8, Kavalieros in view of Jangjian teaches the semiconductor device of claim 1, wherein the first diffusion barrier layer comprises a metal nitride layer (Jangjian, 250 as TiN, fig8, [39]).
Re claim 21, Kavalieros teaches a semiconductor device (fig4B), comprising:
a substrate (410, fig4B, [69]);
a gate structure (420 and 460, fig4A and 4B, [69, 74]).
Kavalieros does not explicitly show an oxide layer disposed on the substrate, a first diffusion barrier layer disposed on the oxide layer, and a metal layer disposed on the first diffusion barrier layer;
Jangjian teaches a gate structure (220, fig8, [18]), comprising:
an oxide layer (222, fig8, [19]) disposed on the substrate, a first diffusion barrier layer (250, fig8, [39]) disposed on the oxide layer, and a metal layer (246, fig8, [34]) disposed on the first diffusion barrier layer;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kavalieros and Jangjian to replace Kavalieros 420 with Jangjian 222-250 and Kavalieros 460 with Jangjian 242-246. The motivation to do so is to reduce leakage current and improve device performance (Jangjian, [37, 39]).
Kavalieros in view of Jangjian teaches a gate spacer (Kavalieros, 430a/b, fig4B, [71]) disposed on the first diffusion barrier layer (Jangjian 250 added as top part of Kavalieros 420 in fig4B); and
a source/drain region (Kavalieros, 417/419, fig4B, [74]) adjacent to the gate structure (Kavalieros, 420 and 460, fig4A and 4B, [69, 74]), wherein a top surface of the source/drain region (part of Kavalieros 417/419 in contact with lower part of 420 as the oxide layer Jangjian 222, Kavalieros 420 replaced by 222-224-250 of Jangjian, fig4B) is disposed below the first diffusion barrier layer (Jangjian 250 added as top part of Kavalieros 420 in fig4B).
Re claim 22, Kavalieros in view of Jangjian teaches the semiconductor device of claim 21, further comprising a high-k oxide layer disposed between the oxide layer and the first diffusion barrier layer (Kavalieros 420 replaced by Jangjian 222-250 and 224 as high-K between oxide 222 and barrier 250, fig4B).
Re claim 23, Kavalieros in view of Jangjian teaches the semiconductor device of claim 21, wherein the gate spacer (Kavalieros, 430a/b, fig4B, [71]) is disposed on a top surface of the first diffusion barrier layer (Jangjian 250 added as top part of Kavalieros 420 in fig4B).
Re claim 24, Kavalieros in view of Jangjian teaches the semiconductor device of claim 21, wherein the gate spacer (Kavalieros, 430a/b, fig4B, [71]) is disposed on a top surface of the oxide layer (Jangjian 222 added as bottom part of Kavalieros 420 in fig4B) and along a sidewall of the metal layer (Kavalieros 460 replaced by Jangjian 242-246 and 246 as Al, fig4B).
Re claim 26, Kavalieros in view of Jangjian teaches the semiconductor device of claim 21, further comprising a second diffusion barrier layer (Jangjian, 242, fig8, [26]) disposed on the first diffusion barrier layer (Jangjian, 250, fig8, [39]), wherein the second diffusion barrier layer comprises a tantalum nitride layer and aluminum dopants in the tantalum nitride layer (Jangjian, 242 as TaAlN or TaAlCN, fig8, [26]).
Re claim 27, Kavalieros teaches a semiconductor device (fig4B), comprising:
a substrate (410, fig4B, [69]);
a fin structure (413, fig4B, [73]) disposed on the substrate;
Kavalieros does not explicitly show a high-k oxide layer disposed on the fin structure; a metal nitride layer disposed on the high-k oxide layer;
Jangjian teaches a gate structure (220, fig8, [18]), comprising:
a high-k oxide layer (224, fig8, [39]) disposed on the fin structure (channel between 212, fig8, [16]), a metal nitride layer (250 as TiN or 242 as TaAlN, fig8, [26, 39]) disposed on the high-k oxide layer;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kavalieros and Jangjian to replace Kavalieros 420 with Jangjian 222-250 and Kavalieros 460 with Jangjian 242-246. The motivation to do so is to reduce leakage current and improve device performance (Jangjian, [37, 39]).
Kavalieros in view of Jangjian teaches a pair of spacers (Kavalieros, 430a/b, fig4B, [71]) disposed on the metal nitride layer (Jangjian 250 as TiN added as top part of Kavalieros 420 or 242 as TaAlN added as bottom part of Kavalieros 460 in fig4B);
a metal layer (Kavalieros 460 replaced by Jangjian 242-246 and 246 as Al, fig4B) disposed on a portion of the metal nitride layer (Jangjian 250 as TiN added as top part of Kavalieros 420 or 242 as TaAlN added as bottom part of Kavalieros 460 in fig4B in fig4B) uncovered by the pair of spacers (Kavalieros, 430a/b, fig4B, [71]); and
a source/drain region (Kavalieros, 417/419, fig4B, [74]) with a top surface (part of Kavalieros 417/419 in contact with lower part of 420 as the oxide layer Jangjian 222, Kavalieros 420 replaced by 222-224-250 of Jangjian, fig4B) below the metal nitride layer (Jangjian 250 as TiN added as top part of Kavalieros 420 or 242 as TaAlN added as bottom part of Kavalieros 460 in fig4B).
Re claim 28, Kavalieros in view of Jangjian does not explicitly show the semiconductor device of claim 27, wherein the metal nitride layer comprises a tantalum nitride layer and aluminum dopants in the tantalum nitride layer (Jangjian 242 as TaAlN added as bottom part of Kavalieros 460 in fig4B).
Re claim 29, Kavalieros in view of Jangjian teaches the semiconductor device of claim 27, wherein the metal nitride layer comprises a tapered cross-sectional profile (Jangjian 250 added as top part of Kavalieros 420 in fig4B).
Re claim 30, Kavalieros in view of Jangjian teaches the semiconductor device of claim 27, further comprising another metal nitride layer (Jangjian 242 TaAlN added as bottom part of Kavalieros 460 in fig4B) disposed on the metal nitride layer (Jangjian 250 TiN added as top part of Kavalieros 420 in fig4B), wherein materials of the metal nitride layer and the other metal nitride layer are different from each other.
Claim(s) 10 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kavalieros et al.US 2020/0312978 in view of Jangjian et al. US 2015/0054029 and More et al. US 2022/0216327.
Re claim 10, Kavalieros in view of Jangjian does not explicitly show the semiconductor device of claim 1, wherein the first diffusion barrier layer comprises metal dopants with a concentration of about 1 atomic % to about 10 atomic %.
Jangjian teaches the first diffusion barrier layer 250 as a combination of TiN and TaN ([39]).
More teaches diffusion barrier as TaxTiyNz or TixAlyNz with Ti, Ta and Al about 8-35 atomic % ([40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kavalieros, Jangjian and More to adjust the concentration of the metal dopants of the first diffusion barrier to about 1-10 atomic %. The motivation to do so is to reduce effective oxide thickness and improve device reliability, device leakage and control Vt shift due to metal diffusion (More, [16]).
Re claim 25, Kavalieros in view of Jangjian does not explicitly show the semiconductor device of claim 21, wherein the first diffusion barrier layer comprises a titanium nitride layer and aluminum dopants in the titanium nitride layer.
More teaches diffusion barrier as TixAlyNz with Al about 8-35 atomic % ([40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kavalieros, Jangjian and More to adjust the concentration of the metal dopants of the first diffusion barrier to about 1-10 atomic %. The motivation to do so is to reduce effective oxide thickness and improve device reliability, device leakage and control Vt shift due to metal diffusion (More, [16]).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to form a gate structure with reduced leakage current occurring in the source/drain region.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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