DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
1. Claims 2-21 are present for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
2. Claims 2-4, 13 & 21 are rejected under pre-AIA 35 U.S.C. 102(a) as being
anticipated by Shi et al (US 7,454,586).
. Claims 2 & 13, Shi et al (Fig. 4) shows a memory device and method for a controller (or array logic) to control a DRAM memory core, which includes the necessary steps for sending self-refresh command to DRAM arrays 42 for refreshing a plurality of memory banks during self-refresh mode, and also a reading step for reading the temperature information stored as a register value and transfer that temperature information onto the external bus to the memory controller and/or other processors as these techniques are also considered as well-known to a skilled person in this art as well.
For example, Fig. 4 shows usage of a register 54 for storing temperature values measured by temperature sensor 62, as “temperature threshold values” so that the controller can readout using the “temperature read command” 52 and convey these temperature values out to the external I/O bus or channel using I/O buffers (54 & 56) and read/write FIFOs (50 ^ 58).
Claim 3-4, 14-15 these read-out temp values can be used to by the memory controller adjust the refresh rates which can properly maintain the functionality of the whole DRAM array, and Fig. 4 shows a sideband bus (or data DQ channel 24) interfacing between DRAM array and an external controller as also well-known techniques in this art.
Claim 21, the clock interface is inherently used by all the system components shown in Fig. 6, including DRAM controller and processors, if any, as all these interfaces are considered as conventional and well-known means in this art for operating memory commands and memory operations as well. See more details from Lee patent below:
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[AltContent: textbox (Temperature values stored in register can be read out to external side bus during self-refresh mode using “temp read command” 52, so as to adjust refresh frequency up of down, etc. )]
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3. Claims 2-4, 13-15 & 21 are rejected under pre-AIA 35 U.S.C. 102(a) as being
anticipated by Lee (US 7,590,020).
Claims 2 & 13, Lee et al (Fig. 4) shows a memory device and method for a controller (or memory hub control block 226) to control a DRAM memory devices 230 by a clock/data interface 221, which includes the necessary steps for sending self-refresh command to DRAM arrays 230 for refreshing a plurality of memory banks during self-refresh mode, and also a reading step for reading the temperature information stored as a register value and transfer that temperature information onto the external bus to the memory controller and/or other processors as these techniques are also considered as well-known to a skilled person in this art as well.
For example, Fig. 4 shows usage of a register 225 for storing temperature values measured by temperature sensor, as “temperature threshold values” so that the controller can readout using the “temperature read command” from the control hub 226, and convey these temperature values out to the external I/O (bus or SMB I/O channel using the high-speed interface block 222
Claim 3-4, 14-15 these read-out temp values can be used to by the memory controller adjust the refresh rates which can properly maintain the functionality of the whole DRAM array, and Fig. 4 shows a sideband bus (or data SMB channel dedicated
for I/O communications with an external host 210 for example) interfacing between DRAM array and an external controller as also well-known techniques in this art.
Claim 21, Fig. 5A-5B shows prior art usage of a clock signal (CLK) and these clock signal/diagram could be used inherently by all the system components shown in Fig. 6, including DRAM controller and processors, if any, as all these interfaces are considered as conventional and well-known means in this art for operating memory commands and memory operations as well. See more Lee’s details on reading temperature from register using an external host’s command below:
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4. Claims 2-3 & 13-14 are rejected under pre-AIA 35 U.S.C. 102(a) as being
anticipated by Kim et al (US 7,266,0310).
This rejection has been fully discussed in the last office action, and thus not to repeat again here.
Regarding the applicant’s remarks on the new limitations of new claims 2, 13 & 21, it is noted that the claim 1 language of Kim’s patent (see col. 10) clearly recited that “obtaining the temperature information indicative of temperature of memory device, wherein obtaining temperature comprises reading one or more bits in the mode register”, thus inherently imply that the stored temperature values can be read out (or obtained) from a mode register as similar claimed by this instant application as well.
5. Other dependent claims (not mentioned) are tentatively objected as being dependent upon the rejected claims above, but they tentatively contain other/additional novel limitations to the recited structure above, which are not clearly suggested by the prior arts nor seen elsewhere at this time.
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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