DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
1. Claims 2-21 are present for examination, and claim 1 has been canceled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
2. Claims 2-3 & 13-14 are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by Kim et al (US 7,266,031).
Claims 2 & 13, Kim et al (Figs. 2-3) shows a refresh operation for a DRAM memory array (200 & 220, see Fig. 2) by a memory controller 301 (see Fig. 3), wherein a self-refresh command is sent from controller to a refresh control circuit 305 using a mode register 320 (Fig. 3); and during the self-refresh mode, the mode register can store a temperature values (i.e., binary codes TD[0:N], Fig. 2) from a temperature sensor 303 into mode register, and such store temperature value TD [0:N] would then be used later by the controller to conveyed to the DRAM memory by the refresh circuitry 305. Fig. 2 shows such temperature control signals TD[0:N] would be used to generate the refresh voltage levels for performing the self-refresh as operation claimed. See also cols. 4-5 description and Table 1 for storing four different temperature values TD[0:4] for control different rate of cell refreshing.
PNG
media_image1.png
594
924
media_image1.png
Greyscale
PNG
media_image2.png
720
1134
media_image2.png
Greyscale
Claims 3 & 14, the temperature information are used by the refresh circuit to adjust or control different refresh voltages, thus also adjust different refresh rates (low or high) for different memory cells (having different threshold voltages), thus also to achieve “power saving” purpose and maintain a better cell functionality as claimed.
3. Claims 2-5, 13-16, & 21 are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by Matsumoto et al (US 2002/0191467).
Claims 2, 13 & 21, Matsumoto et al (Figs. 7, 9 & 31) shows a refresh operation for a DRAM memory array (73, Fig. 19) by a memory controller 301 (72, Fig. 19), wherein a self-refresh command is sent from controller to a refresh control circuit 72 using a register 74 (Fig. 3); and during the self-refresh mode, the register can store a temperature values (see temperature table in Fig. 22) from a temperature sensor into said register, and such store temperature signals would then be used later by the controller to conveyed to the DRAM memory by the refresh circuitry (see Figs. 34-37). Fig. 22 shows such temperature control signals would be used to generate the different refresh voltage levels for performing the self-refresh as operation claimed. Additionally, Figs. 8-11 & 32 shows various clock circuits together with refresh timer circuit (31, Fig. 32) for supplying different clock frequencies to the DRAM device (by its bank addresses) for different self-refresh operations.
PNG
media_image3.png
308
560
media_image3.png
Greyscale
PNG
media_image4.png
378
648
media_image4.png
Greyscale
Claims 3 & 14, the temperature information are used by the refresh circuit to adjust or control different refresh voltages, thus also adjust different refresh rates (low or high) for different memory cells (having different threshold voltages), thus also to achieve “power saving” purpose and maintain a better cell functionality as claimed.
Claims 4 & 15. Fig. 19 shows that a dedicated or sideband bus between a controller 72 and the DRAM device 73 for storing & reading the temperature information of the register 74.
Claims 5 & 16, Fig. 24 shows the controller include an address decoder for sending commands to access the DRAM device, and also to use the two address bits (A0 & A1) to change the clock frequency of a clock oscillator circuit (31), from a first frequency to second frequency, so that a second command for self-resh can be operated at a different/second frequency (which depends on the different address bits A0 & A1).
4. Claims 2-5, 13-16, & 21 are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by Furutani et al (US 2010/0195412).
Claims 2, 13 & 21, Furutani et al (Figs. 1-2) shows a refresh operation for a DRAM memory array (1) by a memory controller 301 (72, Fig. 19), wherein a self-refresh command is sent from memory controller 10 to a refresh control circuit 15 using a register 74 (or latch circuits 23 storing encoded temperature information from encoder 19, Fig. 2); and during the self-refresh mode, the register/latch 23 can store a temperature values from a temperature sensor (or temp measure circuit 17, Fig. 1) into said latch/register, and such store temperature signals would then be used later by the controller to conveyed to the DRAM memory by the refresh control circuitry 15. Fig. 5B shows such temperature control signals are encoded as 3-bit codes to be stored in register, and it would be used later to generate the different refresh voltage levels(see Fig. 6A-6B) for performing the self-refresh as operation claimed. Additionally, Fig. 1 shows a clock circuit 14 and Fig. 7-8 shows various refresh periods implemented based on different measured temperature values together with data driver circuit for adjusting and supplying different clock frequencies to the DRAM device in different self-refresh periods as claimed.
PNG
media_image5.png
402
830
media_image5.png
Greyscale
Claims 3 & 14, Figs. 6A-10 shows different temperature information are used by the refresh circuit to adjust or control different refresh voltages, thus also adjust different refresh rates (low or high) for different memory cells (having different threshold voltage), thus also to achieve “power saving” purpose and maintain a better cell functionality as claimed.
Claims 4 & 15. Fig. 4 shows that a dedicated or sideband bus (I/O) between a controller 72 and the DRAM device 73 for storing & reading the temperature information in the register (latch 11).
Claims 5 & 16, Figs. 8 & 10 shows the controller include an address decoder for sending commands to access the DRAM device, and also to use the 3-bit codes to change the clock frequency of a clock oscillator circuit for four different temperature values (i.e., from 25C to 115C) so that a second command for self-resh can be operated at a different/second frequency with a first command if sensed by temperature sensor.
Allowable Subject Matter
5. The following claims are objected as being dependent upon the rejected claims above, but they tentatively contain other novel limitations to the recited structure of the claims 2, 13 or 21 as follows:
- Claims 6-8 & 17-19 recite specific power modes (power-down or power-up) changeable upon either a first command and/or a second command from interface controller, which are not suggested by the teachings above;
- Claims 9 & 20 recite features of “sending self-refresh command to DRAM before it changes to the “power-down” mode, which are not suggested by prior arts above;
- Claims 8 & 10 recite usage of first and second transitions of the power-mode signal for entering and/or existing the self-refresh mode, which are not also not seen elsewhere;
- Claims 11-12 recite the usage of the “parameter information of the command”, such as, i.e., a voltage associated with either second frequency, row address to column address delay and access time for read data, which are not suggested by teachings above.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
Prosecution Insights