DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, including claims 1-14 and 21-26 in the reply filed on June 24, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 8-10, 12, 14, 21, and 23-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hou et al. (2023/0307375, hereafter Hou).
Regarding claim 1, Hou discloses a semiconductor package, comprising: a redistribution structure (72’, Fig. 47, par. 0046); two or more semiconductor dies (84, Fig. 47, par. 0054) connected to a first side of the redistribution structure; an encapsulant (81, Fig. 47, par. 0081) surrounding the two or more semiconductor dies; an integrated passive device (IPD) (74, Fig. 47, par. 0048) connected on a second side of the redistribution structure, the second side being opposite to the first side, wherein the IPD is electrically coupled to the redistribution structure; an interconnect device (30, Fig. 47, par. 0029) connected on the second side of the redistribution structure and electrically coupled to the redistribution structure; and two or more external connections (114/122, Fig. 47, par. 0093) on the second side of the redistribution structure and electrically coupled to the redistribution structure.
Regarding claim 4, Hou discloses a semiconductor package wherein: each of the two or more semiconductor dies (84, Fig. 47) comprises die connectors (84 top, Fig. 47) at a front side of the two or more semiconductor dies, and wherein the first side of the redistribution structure (72’, Fig. 47) is electrically coupled to the two or more semiconductor dies via the die connectors; and the second side of the redistribution structure comprises under-bump metallizations (UBMs) (68, Fig. 8, 47; par. 0046), and wherein the interconnect device (30, Fig. 47), the IPD (74, Fig. 47), and the two or more external connections (114/122, Fig. 47, par. 0093) are electrically coupled to the redistribution structure via the UBMs.
Regarding claim 5, Hou discloses a semiconductor package wherein the two or more external connections comprise a conductive pillar (114, Fig. 47, par. 0109) and a solder connection (122, Fig. 47, par. 0109) that is coupled to the conductive pillar, and wherein the IPD (74, Fig. 47) and the interconnect device (30, Fig. 47) have a height that is smaller than a height of solder connections of the external connections.
Regarding claim 6, Hou discloses semiconductor package further comprising: a package substrate (123, Fig. 47, par. 0109) connected to the external connections (114/122, Fig. 47), where the package substrate comprises connection pads (124, Fig. 47, par. 0109), and wherein the solder connections (122, Fig. 47) of the external connections are connected to the connection pads; and an underfill (125/77/42, Fig. 47) material between the package substrate and the redistribution structure (72’, Fig. 47), wherein the underfill material surrounds the IPD (74, Fig. 47), the interconnect device (30, Fig. 47), and the external connections.
Regarding claim 8, Hou discloses a semiconductor package, comprising: a redistribution structure (72’, Fig. 47); a first semiconductor die (84 left, Fig. 47) and a second semiconductor die (84 right, Fig. 47) attached to a first side of the redistribution structure; an interconnect device (30, Fig. 47) connected on a second side of the redistribution structure, wherein the interconnect device is electrically coupled to the first semiconductor die and the second semiconductor die; and two or more external connections (114/122, Fig. 47) on the second side of the redistribution structure, wherein the two or more external connections extend along sidewalls of the interconnect device.
Regarding claim 9, Hou discloses a semiconductor package further comprising: an encapsulant (92, Fig. 17, 47; par. 0059) surrounding the first semiconductor die (84 left, Fig. 17) and the second semiconductor die (84 right, Fig. 17).
Regarding claim 10, Hou discloses a semiconductor package further comprising: an integrated passive device (IPD) (74, Fig. 47) connected on the second side of the redistribution structure (72’, Fig. 47), wherein the IPD device is at least partially overlapping the first semiconductor die or the second semiconductor die (84 left/right) and is electrically coupled to the first semiconductor die and the second semiconductor die (Fig. 47).
Regarding claim 12, Hou discloses a semiconductor package wherein the external connections comprise a conductive pillar (114) and a solder connection (122) connected to the conductive pillar, the semiconductor package further comprising: a package substrate (123) connected to the external connections, where the package substrate comprises connection pads (124), wherein the solder connections of the external connections are connected to the connection pads; and an underfill material (125/77/42) formed between the package substrate and the redistribution structure (72’), wherein the IPD (74) and the interconnect device (30) have a height that is smaller than a height of the external connections, and wherein the underfill material surrounds the IPD, the interconnect device, and the external connections (Fig. 47).
Regarding claim 14, Hou discloses a semiconductor package wherein: the redistribution structure (72’) comprises vias having a U-turn structure (Fig. 47).
Regarding claim 21, Hou discloses a package comprising; a redistribution structure (72’); a first semiconductor die (84 left) and a second semiconductor die (84 right) bonded to a top surface of the redistribution structure; an interconnect die (30) bonded to a bottom surface of the redistribution structure, wherein the interconnect die electrically couples the first semiconductor die to the second semiconductor die; conductive connectors (114) on the bottom surface of the redistribution structure; a package substrate (123) bonded to the redistribution structure by the conductive connectors; and a first underfill (125/77/42) between the redistribution structure and the package substrate, wherein the first underfill extends along sidewalls of the conductive connectors and the interconnect die (Fig. 47).
Regarding claim 23, Hou discloses a package further comprising an encapsulant (92, Fig. 17, 47) over the redistribution structure (72’, Fig. 47) and surrounding the first semiconductor die (84 left, Fig. 47) and the second semiconductor die (84 right, Fig. 47).
Regarding claim 24, Hou discloses a package wherein the conductive connectors (114/122) extend further beyond the bottom surface of the redistribution structure (72’) than the interconnect die (30) (Fig. 47).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Hou.
Regarding claim 22, in the embodiment discussed above, Hou does not disclose a package further comprising a second underfill between the interconnect die and the redistribution structure, wherein the second underfill is disposed between the interconnect die and the first underfill.
However, in a separate embodiment, Hou teaches a package further comprising a second underfill (40, Fig. 4, par. 0033) between the interconnect die (30, Fig. 4, par. 0033) and the redistribution structure (26, Fig. 4, par. 0033), wherein the second underfill is disposed between the interconnect die and the first underfill (42, Fig. 4, par. 0034).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou’s teaching by implementing a second underfill in order to protect delicate micro-bumps from thermal stress while the outer underfill stabilizes the component.
Claims 2, 3, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hou in view of Chen et al. (2022/0359406, hereafter Chen).
Regarding claim 2, Hou discussed above fails to disclose a semiconductor package wherein a distance between two neighboring semiconductor dies is less than or equal to a maximum extent of the two or more semiconductor dies, and wherein the IPD is at least partially overlapping a first semiconductor die of the two or more semiconductor dies and is at least electrically coupled to the first semiconductor die.
However, Chen teaches a semiconductor package wherein a distance between two neighboring semiconductor dies (54A and 54B) is less than or equal to a maximum extent of the two or more semiconductor dies (Fig. 14A), and wherein the IPD (52, par. 0052) is at least partially overlapping a first semiconductor die (54A, par. 0052) of the two or more semiconductor dies and is at least electrically coupled to the first semiconductor die (Fig. 14A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou with Chen by providing two dies close together and an IPD overlapping and electrically connected to one in order to ensure high speed, low loss signal while optimizing vertical space and minimizing parasitics.
Regarding claim 3, Hou fails to disclose a semiconductor package wherein the interconnect device is at least partially overlapping a first semiconductor die and a second semiconductor die, and wherein the interconnect device is electrically coupled to the first semiconductor die and the second semiconductor die.
However, Chen teaches a semiconductor package wherein the interconnect device (50, par. 0052) is at least partially overlapping a first semiconductor die (54A) and a second semiconductor die (54B), and wherein the interconnect device is electrically coupled to the first semiconductor die and the second semiconductor die (Fig. 14A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou with Chen by providing an interconnect device that overlaps and electrically connects to both die in order to provide localized, high density silicon routing that maximizes communication between chips.
Regarding claim 11, Hou discloses the encapsulant (92, Fig. 17 and 47) surrounds the first and second semiconductor dies (84 left/right).
Hou fails to disclose a semiconductor package, wherein a distance between the first semiconductor die and the second semiconductor die is less than or equal to a maximum extent of the first semiconductor die and the second semiconductor die.
However, Chen teaches a semiconductor package, wherein a distance between the first semiconductor die (54A) and the second semiconductor die (54B) is less than or equal to a maximum extent of the first semiconductor die and the second semiconductor die (Fig. 14A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou with Chen by providing dies that are close together in order to ensure high speed, low loss signal.
Claims 7, 13, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hou in view of Choi (2021/0272930, hereafter Choi).
Regarding claim 7, Hou discussed above fails to disclose a semiconductor package further comprising: a heat conductive layer thermally coupled to a backside of the two or more semiconductor dies; and a heat-dissipating lid thermally coupled to the heat conductive layer.
However, Choi teaches a semiconductor package further comprising: a heat conductive layer (910, Fig. 20, par. 0125) thermally coupled to a backside of the two or more semiconductor dies (400, Fig. 20, par. 0125); and a heat-dissipating lid (920, Fig. 20, par. 0125) thermally coupled to the heat conductive layer.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou with Choi by providing a heat conductive layer thermally coupled to the dies and a heat-dissipating lid in order to rapidly draw and spread heat away from dies while the dissipating layer transfers that heat to surrounding environment.
Regarding claim 13, Hou fails to disclose a semiconductor package further comprising: a heat-dissipating lid mounted on the package substrate and thermally coupled to the first semiconductor die and the second semiconductor die, wherein a heat conductive layer is thermally coupled between the heat-dissipating lid and backsides of the first semiconductor die and the second semiconductor die.
However, Choi teaches a semiconductor package further comprising: a heat-dissipating lid (920) mounted on the package substrate (100) and thermally coupled to the first semiconductor die (400 left) and the second semiconductor die (400 right), wherein a heat conductive layer (910) is thermally coupled between the heat-dissipating lid and backsides of the first semiconductor die and the second semiconductor die (Fig. 20).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou with Choi by providing a heat conductive layer thermally coupled to the dies and a heat-dissipating lid in order to rapidly draw and spread heat away from dies while the dissipating layer transfers that heat to surrounding environment.
Regarding claim 25, Hou fails to disclose a package further comprising: a heat dissipation feature attached to the package substrate, wherein the heat dissipation feature overlaps the first semiconductor die and the second semiconductor die.
However, Choi teaches a package further comprising: a heat dissipation feature (920) attached to the package substrate (100), wherein the heat dissipation feature overlaps the first semiconductor die (400 left) and the second semiconductor die (400 right) (Fig. 20).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou with Choi by providing a heat dissipation feature attached to the substrate and overlapping the dies in order to act as a mechanical stiffener which prevents warpage and protects dies from the environment.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hou in view of Choi as applied to claim 25 above, and further in view of Liu (2024/0234273, hereafter Liu) and Wu et al. (2023/0369274, hereafter Wu).
Regarding claim 26, Hou discussed above fails to disclose a package further comprising: a memory die bonded to the package substrate.
However, Liu teaches a package further comprising: a memory die (130, Fig. 19, par. 0054) bonded to the package substrate (126, Fig. 19, par. 0054).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou with Liu by providing a memory die bonded to the package substrate in order to bypass memory wall, providing massive data bandwidth with less power consumption and required physical space.
Hou and Liu fail to disclose the memory die extends into an opening in the heat dissipation feature.
However, Wu teaches the memory die extends into an opening (1062, Fig 33, par. 0113) in the heat dissipation feature (1060, Fig. 33, par. 0113).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Hou and Liu with Wu by providing an opening through which the memory die extends in order to allow external cooling system via direct thermal contact with silicon.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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/C.M.B./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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