DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP7303971, an English computer translation (CT) is provided, in view of Thedjoisworo et al (US 2016/0064212).
JP7303971 teaches a method of epitaxial deposition for manufacturing a semiconductor substrate comprising forming high-aspect ratio trenches in a stripe pattern in a silicon substrate and the trenches are backfilled with a silicon epitaxial growth layer, wherein the aspect ratio is 10 or more, or 20 or more with explicit examples of an aspect ratio of 10 and 12 (CT [0001], [0010]-[0018], [0029], [0044], [0050]). JP7303971 teaches the trench filling epitaxial growth was carried out at 1000°C and a pressure of 730 torr to 750 torr (CT [0033], [0061]), which clearly suggests depositing a material in the openings with an aspect ratio of greater than 5:1 at a pressure of about 700 to 800 Torr because overlapping ranges are prima facie obvious (MPEP 2144.05).
JP7303971 teaches a trench substrate is placed in an epitaxial growth apparatus and heat treated at 1100°C in a hydrogen atmosphere to remove a native oxide from the silicon substrate, and then the substrate is cooled to the epitaxial growth temperature and the epitaxial layer is vapor phase grown (CT [0030], [0064]). JP7303971 does not teach plasma pre-cleaning a substrate having openings, wherein the plasma pre-cleaning is performed at a pressure of less than 5 torr.
In a method of cleaning a substrate, Thedjoisworo et al teaches a substrate can be provided in a plasma processing chamber, where the substrate includes the plurality of high-aspect ratio openings, the plurality of high-aspect ratio openings are defined by vertical structures; and removing native silicon oxide using hydrogen based plasma ([0005]-[0009]). Thedjoisworo et al also teaches plasma can form hydrogen radicals to etch native silicon oxides at a pressure of less than about 10 mTorr to remove silicon oxide at the bottom of high aspect ratio openings with minimal damages to vertical structures ([0073]-[0074]) . Thedjoisworo et al also teaches conditions of the plasma processing chamber can be configured to optimize removal of the silicon at the bottom of the high-aspect ratio openings, wherein the pressure in the plasma processing chamber can be between about 10 mTorr and about 3500 mTorr, and the temperature can be between about 5° C and about 200°C ([0081]). Overlapping ranges are prima facie obvious (MPEP 2144.05).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify JP7303971 by using a plasma treatment at a pressure lower than 5 Torr to remove a native oxide from high aspect ratio openings, as taught by Thedjoisworo et al, to minimize damage to vertical structures and clean at lower temperatures.
Referring to claim 7, see the remarks above regarding claim 1.
Claim(s) 2-6 and 8-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP7303971, an English computer translation (CT) is provided, in view of Thedjoisworo et al (US 2016/0064212), as applied to claim 1 and 7 above, and further in view of Bao et al (US 2018/0076065).
The combination of JP7303971 and Thedjoisworo et al teaches all of the limitations of claims 2 and 8, as discussed above, except disposing the substrate in a factory interface, and transfer the substrate from the factory interface to the processing chamber.
In a integrate system for semiconductor processing, Bao et al teaches a cluster tool includes a pre-clean chamber, an etch chamber, one or more pass through chambers, one or more outgassing chambers, a first transfer chamber, a second transfer chamber, and one or more process chambers for epitaxial deposition (Abstract). Bao et al teaches a factory interface 212 is connected to a transfer chamber ([0027]; Fig 2). Bao et al teaches a substrate is first transferred to the cleaning chamber 214 where a cleaning process is performed to remove native oxide and contaminants such as carbon or hydrocarbons from the substrate surface and transferring to an epitaxial deposition chamber (Fig 1-2; [0014]-[0024]). Bao et al teaches clustering the native oxide removal chamber along with the etching of silicon and epitaxial deposition also leads to a reduction in oxygen contaminants; therefore, the integrated system advantageously provides for an improved semiconductor device and quality of deposited epitaxial film ([0029]-[0030]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of JP7303971 and Thedjoisworo et al by using the cluster tool having a factory interface, transfer chamber, cleaning chamber and deposition chamber, and disposing the substrate in a factory interface, and transfer the substrate from the factory interface to the processing chamber in the as taught by Bao et al, to reduce contamination and improve device quality.
Referring to claims 3 and 9, the combination of JP7303971, Thedjoisworo et al and Bao et al teaches the plasma pre-cleaning occurs in a first processing chamber of a substrate processing system; and the epitaxial deposition occurs in a second processing chamber of the substrate processing system (Bao Fig 2, [0026]-[0030] teaches a cluster tool comprising a preclean chamber, a transfer chamber and a processing chamber for epitaxy).
Referring to claim 4, the combination of JP7303971, Thedjoisworo et al and Bao et al teaches transferring the substrate from the first processing chamber to the second processing chamber (Bao Fig 2, [0026]-[0030] teaches a cluster tool comprising a preclean chamber, a transfer chamber and one or more processing chamber for epitaxy).
Referring to claim 5, the combination of JP7303971, Thedjoisworo et al and Bao et al teaches a transfer chamber between the first processing chamber and the second processing chamber has a pressure of about 700 Torr to about 800 Torr (Bao Fig 2, [0026]-[0030] teaches a cluster tool comprising a preclean chamber, a transfer chamber and a processing chamber for epitaxy; JP7303971 teaches the trench filling epitaxial growth was carried out at 1000°C and a pressure of 730 torr to 750 torr (CT [0033], [0061]). Overlapping ranges are prima facie obvious (MPEP 2144.05).
Referring to claims 6 and 12, the combination of JP7303971, Thedjoisworo et al and Bao et al teaches the plasma pre-cleaning comprises a pre-clean temperature of about 100° C. to about 300° C (Thedjoisworo teaches plasma cleaning wherein the temperature can be between about 5° C and about 200°C ([0081])); the deposition of the material comprises a deposition temperature of about 400° C. to about 1200° C (JP7303971 teaches the trench filling epitaxial growth was carried out at 1000°C). The combination of JP7303971, Thedjoisworo et al and Bao et al does not explicitly teach the deposition of the material comprises a deposition time of about 100 seconds to about 5000 seconds. The duration/deposition time is a result effective variable. Therefore, It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of JP7303971, Thedjoisworo et al and Bao et al to have a deposition time of about 100 seconds to about 5000 seconds to deposit a desired thickness of epitaxial material.
Referring to claim 10, the combination of JP7303971, Thedjoisworo et al and Bao et al teaches transferring the substrate from the first processing chamber to the second processing chamber and one or more additional (third) processing chambers (Bao Fig 2, [0026]-[0030] teaches a cluster tool comprising a preclean chamber, a transfer chamber and one or more processing chamber for epitaxy).
Referring to claim 11, the combination of JP7303971, Thedjoisworo et al and Bao et al teaches a transfer chamber between the first processing chamber and the second processing chamber has a pressure of about 700 Torr to about 800 Torr; and one or more additional (third) processing chambers (Bao Fig 2, [0026]-[0030] teaches a cluster tool comprising a preclean chamber, a transfer chamber and a processing chamber for epitaxy; JP7303971 teaches the trench filling epitaxial growth was carried out at 1000°C and a pressure of 730 torr to 750 torr (CT [0033], [0061]). Overlapping ranges are prima facie obvious (MPEP 2144.05).
Referring to claim 13, see the remarks above regarding the plurality of chambers; and the processing system performing the plasma pre-cleaning and epitaxial deposition. The combination of JP7303971, Thedjoisworo et al and Bao et al teaches a process system that can be used to perform the method (Bao [0025]-[0030], Fig 2), which clearly suggests a process controller because a controller would be required to perform the process within the processing system. Furthermore, a process controller that is programmed/configured to execute the process of claims 1-12 would have been obvious to one of ordinary skill in the art at the time of filing to automate apparatus to execute the process taught by the combination of JP7303971, Thedjoisworo et al and Bao et al.
Referring to claim 14-20, these claims are directed to an apparatus and merely further limit the apparatus by claiming the method limitations which are taught by the combination of JP7303971, Thedjoisworo et al and Bao et al, as discussed above in regards to claim 1-12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Delfino et al (US 5,789,318) teaches removal of the native oxide from the Si surface by exposure to hydrogen at high temperature, or by exposure to a hydrogen plasma for a short time (col 2, ln 55 to col 3, ln 20).
Park et al (KR20050050713A), an English computer translation (CT2) is provided, teaches a silicon substrate, forming a contact hole; performing hydrogen plasma treatment on the cleaned substrate resultant at a temperature of 200 to 600°C and a pressure of several mTorr to several Torr to remove a native oxide film at the substrate interface; and growing an epitaxial silicon layer at the substrate interface (CT pages 4-6). Overlapping ranges are prima facie obvious (MPEP 2144.05).
Kryliouk (US 2010/0273290) teaches a system controller 260 controls activities and operating parameters of the processing system 200; the system controller 260 includes a computer processor and a computer-readable memory coupled to the processor; and the processor executes system control software, such as a computer program stored in memory ([0030]).
Li et al (US 2020/0013624) teaches a controller is programmed to execute a plurality of instructions for the operation of the system 100 to fabricate devices, including operation of the central transfer robot 116 as well as operation of the chambers 102-110 and a loading chamber 114 (Fig 1; [0018]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW J SONG whose telephone number is (571)272-1468. The examiner can normally be reached Monday-Friday 10AM-6PM.
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/ Primary Examiner, Art Unit 1714