DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, corresponding to claims 17-36, in the reply filed on June 22, 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-21, 23-26, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2019/0157144, hereafter Lee) in view of Kojima et al. (JP-2008/300568, hereafter Kojima).
Regarding claim 17, Lee discloses a manufacturing method of a semiconductor device, comprising: forming an interconnect structure (par. 0010) comprising: forming a conductive layer (19, Fig. 4) in a dielectric layer (12, Fig. 4, par. 0011); performing a first thermal treatment (20, Fig. 4, par. 0017) on the conductive layer, … and performing a second thermal treatment (par. 0037) after the first thermal treatment.
Lee fails to disclose during the first thermal treatment, a metal oxidation layer containing a first metal element at a surface of the conductive layer is reduced, forming a second metal oxide layer containing a second metal element; wherein during the second thermal treatment, another metal oxidation layer containing the first metal element and formed after the first thermal treatment is reduced, forming another metal oxide layer containing the second metal element.
However, Kojima teaches during the first thermal treatment, a metal oxidation layer (87, Fig. 4e) containing a first metal element (par. 0047) at a surface of the conductive layer is reduced (par. 0046), forming a second metal oxide layer (par. 0045, 0049) containing a second metal element (par. 0045); wherein during the second thermal treatment, another metal oxidation layer containing the first metal element and formed after the first thermal treatment is reduced, forming another metal oxide layer containing the second metal element (par. 0045-0046, 0049).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Kojima by performing a reduction process with two metal elements in order to achieve self-aligned, atomic-scale metal capping which improves electromigration resistance and device reliability without other complex steps.
Regarding claim 18, Lee fails to disclose a manufacturing method wherein the first metal element is copper and the second metal element is manganese.
However, Kojima teaches a manufacturing method wherein the first metal element is copper and the second metal element is manganese (par. 0045).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Kojima by providing copper as the first metal and manganese as the second metal because manganese automatically migrates during heating which maximizes the volume and usage of copper while preventing shorting and electromigration.
Regarding claim 19, Lee fails to disclose a manufacturing method wherein forming the conductive layer in the dielectric layer comprises: forming a seed layer in an opening of the dielectric layer, wherein the second metal element is incorporated into a material of the seed layer; and forming a conductive material layer on the seed layer, wherein during the conductive layer is formed, the second metal element diffuses into the conductive material layer.
However, Kojima teaches a manufacturing method wherein forming the conductive layer in the dielectric layer comprises: forming a seed layer (86, Fig. 4, par. 0045) in an opening (85, Fig. 4) of the dielectric layer (84, Fig. 4), wherein the second metal element is incorporated into a material of the seed layer (par. 0045); and forming a conductive material layer (87, Fig. 4e) on the seed layer, wherein during the conductive layer is formed, the second metal element diffuses into the conductive material layer (par. 0049).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Kojima by providing a seed layer in the dielectric such that the second metal diffuses into the conductive material in order to create a self-doped interconnect to maximize electromigration resistance and adhesion while keeping bulk electrical resistance as low as possible.
Regarding claim 20, Lee discloses a manufacturing method further comprising: performing a planarization process (C1, Fig. 5, par. 0020) after the first thermal treatment and before the second thermal treatment (par. 0019), wherein the second metal oxide layer (22, Fig. 5) is removed (par. 0025) during the planarization process.
Regarding claim 21, Lee fails to disclose a manufacturing method wherein the second metal element has a higher reactivity with oxygen relative to the first metal element.
However, Kojima teaches a manufacturing method wherein the second metal element has a higher reactivity with oxygen relative to the first metal element (par. 0045).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Kojima by providing a second metal element with a higher reactivity with oxygen than the first in order to drive thermodynamic reduction-oxidation at the interface, extracting oxygen from the insulating material to form a stable oxide barrier while keeping primary conductor pure.
Regarding claim 23, Lee discloses a manufacturing method wherein forming the conductive layer in the dielectric layer comprises: forming a barrier material layer (17, Fig. 6, par. 0014) in an opening (13, Fig. 6) of the dielectric layer (12, Fig. 6); forming a conductive material layer (19, Fig. 6, par. 0014) over the barrier material layer and in the opening of the dielectric layer; performing a planarization process (C2, Fig. 6, par. 0025) on the barrier material layer and the conductive material layer, wherein a metal oxide (23/24, Fig. 6, par. 0028) is formed on the conductive material layer and in the opening of the dielectric layer, and the metal oxide is laterally surrounded (Fig. 6) by the barrier material layer; and removing the metal oxide (par. 0029), wherein a topmost surface of the conductive material layer is recessed from a topmost surface of the barrier material layer (Fig. 9).
Regarding claim 24, Lee discloses a manufacturing method further comprising: forming a transistor (par. 0010-0011) on a substrate (10, Fig. 4, par. 0011); and forming the interconnect structure (par. 0010) over the substrate, wherein the conductive layer is electrically coupled to the transistor (par. 0010-0011).
Regarding claim 25, Lee discloses manufacturing method of a semiconductor device, comprising: forming a first dielectric layer (12, Fig. 4) with a first opening (13, Fig. 4); forming a conductive material layer (19, Fig. 4) over the first dielectric layer and in the first opening, …forming a first metal oxide layer (19 surface, Fig. 4) on the conductive material layer; and reducing the first metal oxide layer (par. 0024) to form a second metal oxide layer (22, Fig. 5).
Lee fails to disclose wherein the conductive material layer comprises a first metal element and a second metal element different from the first metal element; wherein during reducing the first metal oxide layer, the first metal element is regenerated in the conductive material layer, while oxidizing the second metal element.
However, Kojima teaches wherein the conductive material layer (87, Fig. 4, par. 0049) comprises a first metal element (par. 0045) and a second metal element (par. 0045) different from the first metal element; wherein during reducing the first metal oxide layer, the first metal element is regenerated in the conductive material layer, while oxidizing the second metal element (par. 0045-0046, 0049).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Kojima by performing a reduction process using two metal elements wherein the first is regenerated in order to ensure the reactive dopant is uniformly available to drive the reaction, while regenerating ensures that no highly resistive metal oxides remain to degrade electrical conductivity.
Regarding claim 26, Lee discloses a manufacturing method further comprising: removing the second metal oxide layer (22, Fig. 5, par. 0025) to expose the conductive material layer (19, Fig. 6), wherein a third metal oxide layer (24, Fig. 6) is formed on an exposed surface of the conductive material layer and within the first opening; and removing (C3, Fig. 7, par. 0029) the third metal oxide layer to form a first conductive via (19b, Fig. 9), wherein a topmost surface of the first conductive via is formed between a topmost surface and a bottommost surface of the first dielectric layer (12, Fig. 9).
Regarding claim 28, Lee discloses a manufacturing method further comprising: forming a conductive barrier layer (17, Fig. 7) on the first dielectric layer (12, Fig. 7) and in the first opening (13, Fig. 7); forming the conductive material layer (19, Fig. 7) on the conductive barrier layer and filling the first opening; and performing a planarization process (C3, Fig. 7, par. 0030) on the second metal oxide layer (22, Fig. 5) , wherein after performing the planarization process, a surface of the conductive barrier layer and a surface of the conductive material layer are substantially leveled with a topmost surface of the first dielectric layer (Fig. 7).
Claims 22, 30, 31, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kojima as applied to claim 17 above, and further in view of Edelstein et al. (2011/0180309, hereafter Edelstein).
Regarding claim 22, Lee and Kojima, discussed above, fail to disclose a manufacturing method wherein after performing the second thermal treatment, an atomic percentage of the second metal element in the conductive layer is lower than an atomic percentage of the first metal element in the conductive layer.
However, Edelstein teaches a manufacturing method wherein after performing the second thermal treatment, an atomic percentage of the second metal element in the conductive layer (30L, Fig. 3A) is lower than an atomic percentage of the first metal element in the conductive layer (par. 0043).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee and Kojima with Edelstein by performing a thermal treatment wherein afterwards the atomic percentage of the second metal is lower than that of the first metal in the conductive layer in order to prevent electron scattering from impurity atoms, ensuring low resistance in the wire.
Regarding claim 30, Lee discloses manufacturing method of a semiconductor device, comprising: lining a first opening (13, Fig. 4) of a first dielectric layer (12, Fig. 4) with a first conductive barrier layer (17, Fig. 4); forming a first conductive material layer (19, Fig. 4) over the first conductive barrier layer and in the first opening, …forming a first metal oxide layer (22, Fig. 5) on the first conductive material layer.
Lee fails to disclose the first conductive material layer comprises a first metal element and a second metal element different from the first metal element; and performing a reduction process on the first metal oxide layer, wherein the second metal element in the first conductive material layer acts as a reducing agent.
However, Kojima teaches the first conductive material layer comprises a first metal element (par. 0045) and a second metal element (par. 0045) different from the first metal element; and performing a reduction process on the first metal oxide layer, wherein the second metal element in the first conductive material layer acts as a reducing agent (par. 0045-0046).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Kojima by performing a reduction process with two metals in order to ensure the reactive dopant is uniformly available to drive the reaction, thus creating a stable layer while keeping the primary conductor pure.
Lee and Kojima fail to disclose after performing the reduction process, an atomic percentage of the second metal element in the first conductive material layer is lower than an atomic percentage of the first metal element in the first conductive material layer.
However, Edelstein teaches after performing the reduction process, an atomic percentage of the second metal element in the first conductive material layer is lower than an atomic percentage of the first metal element in the first conductive material layer.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee and Kojima with Edelstein by performing a thermal treatment wherein afterwards the atomic percentage of the second metal is lower than that of the first metal in the conductive layer in order to prevent electron scattering from impurity atoms, ensuring low resistance in the wire.
Regarding claim 31, Lee discloses a manufacturing method further comprising: forming a seed material layer (18, Fig. 4) on the first conductive barrier layer (17, Fig. 4), …and forming the first conductive material layer (19, Fig. 4) on the seed material layer.
Lee fails to disclose the seed material layer comprises an alloying material containing the second metal element.
However, Kojima teaches the seed material layer (86, Fig. 4e) comprises an alloying material containing the second metal element (par. 0045).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Kojima by providing an alloy seed layer in order to ensure the reactive dopant is uniformly available to drive the reaction.
Regarding claim 35, Lee discloses a manufacturing method further comprising: performing a planarization process (C3, Fig. 7) to remove the first metal oxide layer (24, Fig. 6, par. 0029), wherein after performing the planarization process, topmost surfaces of the first conductive material layer (19, Fig. 7) and the first conductive barrier layer (17, Fig. 7) are substantially leveled with a topmost surface of the first dielectric layer (12, Fig. 7); forming a second metal oxide layer (19 surface, Fig. 7) on the topmost surface of the first conductive material layer by reacting the first conductive material layer with oxygen (par. 0024, 0028).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kojima as applied to claim 25 above, and further in view of Motoyama et al. (2024/0194587, hereafter Motoyama).
Regarding claim 27, Lee and Kojima, discussed above, fail to disclose a manufacturing method further comprising: forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises a second opening exposing the first conductive via; and forming a second conductive via in the second opening, wherein the second conductive via is in contact with the first conductive via, and a bottommost surface of the second conductive via is formed between the topmost surface and the bottommost surface of the first dielectric layer.
However, Motoyama teaches a manufacturing method further comprising: forming a second dielectric layer (902, Fig. 11) on the first dielectric layer (104, Fig. 11), wherein the second dielectric layer comprises a second opening (402, Fig. 11) exposing the first conductive via (302, Fig. 11); and forming a second conductive via (1206, Fig. 12) in the second opening, wherein the second conductive via is in contact with the first conductive via, and a bottommost surface of the second conductive via is formed between the topmost surface and the bottommost surface of the first dielectric layer (Fig. 12).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee and Kojima with Motoyama by providing a top via in contact with a bottom via through a recessed opening in order to remove interfacial contamination and create interlocking, maximizing connectivity and reliability.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kojima as applied to claim 25 above, and further in view of Kato et al. (2023/0411295, hereafter Kato).
Regarding claim 29, Lee and Kojima, discussed above, fail to disclose a manufacturing method further comprising: recessing the surface of the conductive material layer to form a first conductive via; and forming a second conductive via on the first conductive via, wherein a bottom portion of the second conductive via is laterally surrounded by the conductive barrier layer of the first conductive via.
However, Kato teaches a manufacturing method further comprising: recessing the surface of the conductive material layer (22, Fig. 1A) to form a first conductive via (20a/b, Fig. 1A); and forming a second conductive via (30a/b, Fig. 1A) on the first conductive via, wherein a bottom portion of the second conductive via is laterally surrounded (Fig. 1A) by the conductive barrier layer (24, Fig. 1A) of the first conductive via.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee and Kojima with Kato by stacking vias and having the bottom barrier layer surrounding the bottom of the top via in order to provide a redundant conductive path that prevents device failure while ensuring metal remains isolated from dielectric.
Claims 32 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kojima and Edelstein as applied to claim 30 above, and further in view of Motoyama.
Regarding claim 32, Lee discloses manufacturing method further comprising: removing (par. 0029) the first metal oxide layer (22, Fig. 5, par. 0025) to reveal an exposed surface of the first conductive material layer (19, Fig. 7) which is laterally surrounded by the first conductive barrier layer (17, Fig. 7).
Lee, Kojima, and Edelstein, discussed above, fail to disclose forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises a second opening exposing the exposed surface of the first conductive material layer; lining the second opening with a second conductive barrier layer, wherein the second conductive barrier layer is interfaced with the exposed surface of the first conductive material layer; and forming a second conductive material layer on the second conductive barrier layer and in the second opening.
However, Motoyama teaches forming a second dielectric layer (902, Fig. 12) on the first dielectric layer (104, Fig. 12), wherein the second dielectric layer comprises a second opening (1004, Fig. 12) exposing the exposed surface of the first conductive material layer (302, Fig. 12); lining the second opening with a second conductive barrier layer (1202, Fig. 12, par. 0043), wherein the second conductive barrier layer is interfaced with the exposed surface of the first conductive material layer (Fig. 12); and forming a second conductive material layer (1206, Fig. 12) on the second conductive barrier layer and in the second opening.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee, Kojima, and Edelstein with Motoyama by interfacing a second via barrier layer with the first conductive layer in order to block electromigration at metal-to-metal junctions and prevent metal from diffusing into dielectric.
Regarding claim 36, Lee discloses a manufacturing method further comprising: performing a thermal treatment (par. 0037) on the second metal oxide layer (24, Fig. 6), wherein the second metal oxide layer is reduced to form a third metal oxide layer (19 surface, Fig. 7).
Lee fails to disclose during reducing the second metal oxide layer, the first metal element is regenerated, while oxidizing the second metal element in the first conductive material layer.
However, Kojima teaches during reducing the second metal oxide layer, the first metal element is regenerated (par. 0045-0046, 0049), while oxidizing the second metal element in the first conductive material layer (87, Fig. 4e).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Kojima by performing a reduction process wherein the first metal is regenerated in order to ensure that no highly resistive metal oxides remain to degrade electrical conductivity.
Lee, Kojima, and Edelstein fail to disclose removing the third metal oxide layer to form a recessed top surface of the first conductive material layer.
However, Motoyama teaches removing the third metal oxide layer (402, Fig. 10) to form a recessed top surface of the first conductive material layer (302, Fig. 11).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee, Kojima, and Edelstein with Motoyama by removing the oxide layer to form a recessed surface in order to eliminate interfacial contamination and create interlocking, maximizing connectivity and reliability.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kojima, Edelstein, and Motoyama as applied to claim 32 above, and further in view of Kato.
Regarding claim 33, Lee, Kojima, Edelstein, and Motoyama, discussed above, fail to disclose a manufacturing method wherein after removing the first metal oxide layer, a portion of the first metal oxide layer is remained in the first opening and laterally surrounded by the first conductive barrier layer, and lining the second opening with the second conductive barrier layer comprises: lining an inner sidewall of the portion of the first metal oxide layer with the second conductive barrier layer.
However, Kato teaches a manufacturing method wherein after removing the first metal oxide layer, a portion (28, Fig. 1A) of the first metal oxide layer is remained in the first opening (13b, Fig. 1A) and laterally surrounded by the first conductive barrier layer (24, Fig. 1A), and lining the second opening (15, Fig. 1A) with the second conductive barrier layer (34, Fig. 1A) comprises: lining an inner sidewall of the portion of the first metal oxide layer with the second conductive barrier layer.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee, Kojima, Edelstein, and Motoyama with Kato by leaving a portion of the metal oxide to surround the second conductive layer in order to maintain a localized diffusion barrier preventing short circuiting.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kojima and Edelstein as applied to claim 30 above, and further in view of Mountsier et al. (2010/0187693, hereafter Mountsier).
Regarding claim 34, Lee, Kojima, and Edelstein discussed above fail to disclose a manufacturing method further comprising: forming a second dielectric layer with a second opening on the first dielectric layer, wherein topmost surfaces of the first conductive barrier layer and the first conductive material layer are exposed by the second opening; lining the second opening with a second conductive barrier layer, wherein the second conductive barrier layer is interfaced with the topmost surfaces of the first conductive barrier layer and the first conductive material layer; and forming a second conductive material layer on the second conductive barrier layer and in the second opening.
However, Mountsier teaches a manufacturing method further comprising: forming a second dielectric layer (113, Fig. 1D) with a second opening on the first dielectric layer (103, Fig. 1D), wherein topmost surfaces of the first conductive barrier layer (105, Fig. 1D) and the first conductive material layer (109, Fig. 1D) are exposed by the second opening; lining the second opening with a second conductive barrier layer (125, Fig. 1D), wherein the second conductive barrier layer is interfaced with the topmost surfaces of the first conductive barrier layer and the first conductive material layer; and forming a second conductive material layer (127, Fig. 1D) on the second conductive barrier layer and in the second opening.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee, Kojima, and Edelstein with Mountsier by exposing the top surface of the first conductive layer and interfacing it with a second conductive layer in order to create an unbroken protective casing that prevents metal from escaping in to the dielectric while establishing secure contact.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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/C.M.B./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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