DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 June 2026.
Applicant has stated that claims 9-10 read on the elected species, however, the claims contain language which differentiate them from the elected species I for at least the following reasons:
Regarding claims 9-10, the claims feature or are dependent upon claims which feature the limitation “forming a plurality of metal bumps physically contacting the backside redistribution line”, whereas the elected species I as previously set forth is drawn to structures where metal bumps are not connected to other metal bumps. When a plurality of metal bumps are physically contacting a singular redistribution line, the metal bumps are connected by said line. Therefore, the claims 9-10 are differentiated from elected species I.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites “A method comprising: forming a die comprising: … wherein the first through-via and the second through-via are connected to a first integrated circuit device and a second integrated circuit device, respectively, in the die….” It is unclear how the claimed structure could be in a die when forming said structure is part of the process of forming a die. The die is not yet formed during this stage of the process, so it is unclear what it would mean for the claimed connections to be made in said die, rendering the scope of the claim indefinite. For the purpose of examination, the examiner interprets the claim as reciting “A method comprising: forming a die comprising: … wherein the first through-via and the second through-via are connected to a first integrated circuit device and a second integrated circuit device, respectively,
Regarding claim 5, the claim recites “…recessing the first through-via and the second through-via, so that end portions of the first through-via and the second through-via protrude out of the semiconductor substrate….” Recessing means to set back/into or remove material from a thing, namely the first and second through-vias in this instance. It is unclear how recessing said vias would make them protrude from the surrounding semiconductor substrate as claimed. In light of the specification and drawings, it is the examiner’s opinion that the applicant’s intent was to claim recessing of the semiconductor substrate, rather than the through-vias. For the purpose of examination, the examiner interprets the claim as reciting “…recessing
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 21-28 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yu et al. (US 20210193582 A1, hereinafter Y1).
Regarding independent claim 1, Y1 discloses in Y1 FIG. 4-5, 13, 15 and associated text A method comprising: forming a die comprising (the set of the following structures, inter alia, is interpreted as the die; e.g. integrated circuit package 200 as a whole): forming a first through-via and a second through-via extending from a front side of a semiconductor substrate into the semiconductor substrate (conductive vias 154 extend from a side corresponding to the interface between dielectric layer 148 and semiconductor substrate 142, which is interpreted as a front side, and extends into semiconductor substrate 142), wherein the first through-via and the second through-via are connected to a first integrated circuit device and a second integrated circuit device, respectively (vias 154 are respectively connected to integrated circuit devices through contact pads 146, die connectors 152 of IC die 140, and die connectors 122 of IC die 110, which are connected to the respective integrated circuits of the first IC die 110 (Y1 [0022])); performing a backside grinding process to reveal the first through-via and the second through-via (semiconductor substrate 142 is ground to expose vias 154 (Y1 [0053])); and forming a backside redistribution line physically joining to both of the first through-via and the second through-via (“front-side” redistribution structure 240, which is interpreted as a backside redistribution structure, comprises several redistribution lines, of which, at least one is explicitly depicted as connecting two vias 154, as shown in Y1 FIG. 15).
Regarding dependent claim 2, Y1 further discloses in Y1 FIG. 18A and associated text The method of claim 1 further comprising bonding the die to a package component (package substrate 400), wherein the package component comprises a middle redistribution line (400 comprises metallization layers (not shown) under bond pads 402 (Y1 [0082]), which are interpreted as a middle redistribution line), wherein the middle redistribution line is electrically connected to both of the backside redistribution line of the die (“conductive connectors 258 connect the package substrate 400, including metallization layers in the package substrate 400, to the integrated circuit package 200, including metallization patterns of the redistribution structure 240” (Y1 [0083])) and a third through-via penetrating through the semiconductor substrate (A third via of vias 154, which penetrates through 142, and which is interpreted as connecting to 400 and its middle redistribution line by a pathway off-plane with respect to the cross-section shown in Y1 FIG. 18A, as supported by Y1 [0063], which states that vias 154 are electrically connected to UBMs 256 and, by extension, the middle redistribution line), and wherein the third through-via is electrically connected to a third integrated circuit (as interpreted above, each of vias 154 are connected to respective integrated circuits; see also Y1 [0022]).
Regarding dependent claim 3, Y1 further discloses in Y1 FIG. 18A and associated text The method of claim 2, wherein the package component comprises an under-bump metallurgy physically contacting a solder region (bond pads 402 contact conductive connectors 258, which are solder balls (Y1 [0064]), therefore considered a solder region), wherein a metal bump of the die is between, and physically joining to the solder region and the backside redistribution line (portions of UBMs 256 over dielectric layer 254 are considered metal bumps (Y1 [0063]) and are between and physically joined to 258 and 240).
Regarding dependent claim 4, Y1 further discloses in Y1 FIG. 15 and associated text The method of claim 1, wherein the first integrated circuit device and the backside redistribution line are on opposite sides of the semiconductor substrate (the IC devices, as interpreted above, are in IC die 110, which is on an opposite (bottom side, as shown in Y1 FIG. 15) side of 142 with respect to 240 (top side in Y1 FIG. 15)).
Regarding dependent claim 5, Y1 further discloses in Y1 FIG. 14 and associated text The method of claim 1 further comprising, after the backside grinding process, recessing so that end portions of the first through-via and the second through-via protrude out of the semiconductor substrate (154 protrudes from 142 after a step of recessing 142 (Y1 [0054]), which follows the backside grinding step); and forming a dielectric isolation layer, wherein the end portions are in the dielectric isolation layer (ends of 154 are in barrier layer 224, which is a dielectric material (Y1 [0054])).
Regarding dependent claim 6, Y1 further discloses in Y1 FIG. 15 and associated text The method of claim 5, wherein the backside redistribution line physically contacts the dielectric isolation layer (240 contacts 224; see also Y1 FIG. 14, where 224 is labeled).
Regarding dependent claim 7, Y1 further discloses in Y1 FIG. 15 and associated text The method of claim 1, wherein the backside redistribution line comprises a metal pad and an elongated metal line connecting to the metal pad, and the metal pad physically contacts both of the first through-via and the second through-via (as shown in annotated Y1 FIG. 15 below).
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Regarding dependent claim 8, Y1 further discloses in Y1 FIG. 15 and associated text The method of claim 1, wherein the backside redistribution line comprises a metal pad and an elongated metal line connecting to the metal pad, and the elongated metal line physically contacts both of the first through-via and the second through-via (as shown in annotated Y1 FIG. 15 below).
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Regarding independent claim 21, Y1 discloses in Y1 FIG. 4-5 and 15 and associated text A method comprising: forming a die comprising (the set of the following structures, inter alia, is interpreted as the die; e.g. integrated circuit package 200 as a whole): forming a first integrated circuit device and a second integrated circuit device on a front side of a semiconductor substrate (IC die 110 comprises integrated circuits (Y1 [0022]), including at least a first and second integrated circuit, and 110 is at a side of semiconductor substrate 142 of IC die 140, which is interpreted as a front side of a semiconductor substrate and the step of attaching 110 to 140, as shown in Y1 FIG. 4-5 is interpreted as forming said first and second integrated circuits on a front side of 142); forming a first through-via and a second through-via penetrating through the semiconductor substrate (conductive vias 154 penetrate through semiconductor substrate 142), wherein the first through-via and the second through-via are connected to the first integrated circuit device and the second integrated circuit device, respectively (vias 154 are respectively connected to integrated circuit devices through contact pads 146, die connectors 152 of IC die 140, and die connectors 122 of IC die 110, which are connected to the respective integrated circuits of the first IC die 110 (Y1 [0022])); and forming a first backside redistribution line on a backside of the semiconductor substrate, wherein the first backside redistribution line physically contacts both of the first through-via and the second through-via (“front-side” redistribution structure 240, which is interpreted as a backside redistribution structure, comprises several redistribution lines, of which, at least one is explicitly depicted as physically contacting two vias 154, as shown in Y1 FIG. 15).
Regarding dependent claim 22, Y1 further discloses in Y1 FIG. 15-16 and associated text The method of claim 21 further comprising: forming a second backside redistribution line on the backside of the semiconductor substrate (240 comprises several backside redistribution lines separate from the first, as it was previously interpreted); forming a first metal bump and a second metal bump contacting the first backside redistribution line and the second backside redistribution line, respectively (portions of UBMs 256 over dielectric layer 254 are considered metal bumps (Y1 [0063]), wherein, e.g., the third and sixth of 256, counting from the left of Y1 FIG. 16, correspond to the claimed first and second metal bump, respectively, which contact the first and a second redistribution line of 240, respectively); and forming a first solder region and a second solder region contacting the first metal bump and the second metal bump, respectively (conductive connectors 258 are solder balls (Y1 [0064]), which contact first and second metal bumps of 256, respectively, as interpreted).
Regarding dependent claim 23, Y1 further discloses in Y1 FIG. 18A and associated text The method of claim 22 further comprising bonding a redistribution structure to the die (package substrate 400), wherein the redistribution structure comprises: a first under-bump metallurgy and a second under-bump metallurgy contacting the first solder region and the second solder region, respectively (bond pads 402, interpreted as under-bump metallurgies, contact respective first and second solder regions 258); and a middle redistribution line contacting both of the first under-bump metallurgy and the second under-bump metallurgy (400 comprises metallization layers under 402 (Y1 [0082]), which are interpreted a middle redistribution line, which makes at least indirect contact with the first and second UBMs of 402 through intervening layers of 400).
Regarding dependent claim 24, Y1 further discloses in Y1 FIG. 4 and associated text The method of claim 21, wherein the die further comprises: a first metal pad and a second metal pad on the front side of the semiconductor substrate and contacting the first through-via and the second through-via, respectively (contact pads 146 contact vias 154).
Regarding dependent claim 25, Y1 further discloses in T1 FIG. 5 and associated text The method of claim 24, wherein the die further comprises: a first electrical path and a second electrical path electrically connecting the first metal pad and the second metal pad to the first integrated circuit device and the second integrated circuit device, respectively (individual pads 146 are connected to the first and second IC device through die connectors 152 of IC die 140 and die connectors 122 of IC die 110, which are connected to the respective integrated circuits of the first IC die 110 (Y1 [0022])).
Regarding independent claim 26, Y1 discloses in Y1 FIG. 4-5 and 15 and associated text A method comprising: forming a die comprising (the set of the following structures, inter alia, is interpreted as the die; e.g. integrated circuit package 200 as a whole): forming a first integrated circuit and a second integrated circuit at a front side of a semiconductor substrate (IC die 110 comprises integrated circuits (Y1 [0022]), including at least a first and second integrated circuit, and 110 is at a side of semiconductor substrate 142 of IC die 140, which is interpreted as a front side of a semiconductor substrate and the step of attaching 110 to 140, as shown in Y1 FIG. 4-5 is interpreted as forming said first and second integrated circuits at a front side of 142); forming a dielectric isolation layer contacting a back surface of the semiconductor substrate (barrier layer 224, which is a dielectric material (Y1 [0054]), contacts a surface of 142 interpreted as a back surface); and forming a backside redistribution line contacting the dielectric isolation layer (“front-side” redistribution structure 240, which is interpreted as a backside redistribution structure, comprises several redistribution lines, as shown), wherein the backside redistribution line electrically connects the first integrated circuit to the second integrated circuit (at least one redistribution line of 240 is shown – in Y1 FIG. 15 – connecting between two vias 154, which are respectively connected to a first and second integrated circuit device through contact pads 146, die connectors 152 of IC die 140, and die connectors 122 of IC die 110, which are connected to the respective integrated circuits of the first IC die 110 (Y1 [0022])).
Regarding dependent claim 27, Y1 further discloses in Y1 FIG. 4-5 and 15 and associated text The method of claim 26, wherein the die further comprises: a first metal pad and a second metal pad on the front side of the semiconductor substrate and electrically connected to the first integrated circuit and the second integrated circuit, respectively (contact pads 146, which are connected to a first and second IC through die connectors 152 of IC die 140 and die connectors 122 of IC die 110, which are connected to the respective integrated circuits of the first IC die 110 (Y1 [0022])); and a first through-via and a second through-via physically joined to the first metal pad and the second metal pad, respectively (vias 154 are physically joined to their respective contact pads 146, as shown), wherein the first through-via and the second through-via penetrate through the semiconductor substrate (vias 154 penetrate through 142), and are electrically connected to the first integrated circuit and the second integrated circuit through the first metal pad and the second metal pad, respectively (vias 154 are electrically connected to their respective contact pads 146, as shown).
Regarding dependent claim 28, Y1 further discloses in Y1 FIG. 18A and associated text The method of claim 27, wherein the die further comprises a metal bump on the backside redistribution line (portions of UBMs 256 over dielectric layer 254 are considered metal bumps (Y1 [0063]) and are on 240, including the backside redistribution line, as interpreted), and the method further comprises bonding a package to the die through a solder region (package component 400 is bonded to 200 through conductive connectors 258, which are solder balls).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Y1, and further in view of Tsai et al. (US 20130087925 A1, hereinafter T1).
Regarding dependent claim 11, Y1 discloses the method of claim 1 further comprising. Y1 does not explicitly disclose forming a seal ring in the die; and forming a dummy bump overlapping the seal ring.
However, in the same field of endeavor, T1 discloses in T1 FIG. 1 and associated text forming a seal ring in the die; and forming a dummy bump overlapping the seal ring (dummy bumps 24B overlap seal rings 30 formed in chip 20).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the seal rings and dummy bumps of T1 with the method of Y1 to provide stress absorption and resistance against propagating cracks (T1 [0003], [0005]).
Regarding dependent claim 12, Y1, as modified by T1, further discloses in T1 FIG. 6A and associated text The method of claim 11 further comprising bonding a solder region contacting the dummy bump (connectors 24 are solder balls, which are used to bond (T1 [0010])).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20210167040 A1, pertaining to a die having TSVs connecting to respective integrated circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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