DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, and 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brayerer (US 20180233421 A1).
Regarding claim 1, Bayerer teaches a power semiconductor device arrangement, comprising:
a substrate (400), the substrate comprising:
a ceramic body (418);
a top metal layer (416), disposed on a top surface of the ceramic body; and
a bottom metal layer (412), disposed on a bottom surface of the ceramic body, opposite the top surface [Fig. 17, ¶0047];
a power transistor die (402), comprising a power transistor device, the power transistor die being disposed over the top surface of the substrate [Fig. 17, ¶0046];
a diode die assembly (404), comprising a set of diodes, the diode die assembly disposed over the top surface of the substrate, adjacent to the power transistor die [Fig. 17, ¶0046]; and
The embodiment shown in Fig. 17 of Bayerer doesn’t show the wire bonding connecting the diode die assembly with the power transistor die.
The embodiment shown in Fig. 13 of Brayerer teaches a wire bond connector, having a first end, affixed to an upper surface of the diode die assembly (340), and a second end, affixed to an upper surface of the power transistor die (302) [Fig. 13, ¶¶0024 and 0042, talks about connection between dies and figure shows wire bonds attached to the dies].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the embodiments of Fig. 17 and Fig. 13 of Bayerer together to obtain the claimed display device because the device would have reverse blocking capability as taught by Fig. 13 with the inclusion of the diode die assembly and the power transistor die in the same packaging and Fig. 17 shows a sectional view of an embodiment that further illustrates the diode die assembly and power transistor die in the same packaging.
Regarding claim 2, Bayerer teaches the power semiconductor device arrangement of claim 1, the power transistor die comprising an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET) [¶0015].
Regarding claim 7, Bayerer teaches the power semiconductor device arrangement of claim 1, wherein the second end of the wire bond connector is affixed to a gate electrode (426, Fig. 17), the gate electrode being disposed on an upper surface of the power transistor die (406, Fig. 17) [Figs. 13 and 17, ¶¶0034 and 0042].
Regarding claim 8, Bayerer teaches the power semiconductor device arrangement of claim 7, wherein the power transistor die comprises a main terminal electrode (414, Fig. 17), disposed on a bottom surface of the power transistor die (406, Fig. 17), and wherein the main terminal electrode is bonded to the top metal layer of the substrate (416, Fig. 17) [¶¶0049-0050].
Regarding claim 9, Bayerer teaches the power semiconductor device arrangement of claim 1, wherein the substrate comprises a direct bonded copper (DBC) substrate [¶0055], wherein the top metal layer is a copper layer.
Regarding claim 10, Bayerer teaches the power semiconductor device arrangement of claim 1, the top metal layer comprising a first portion (as seen in Fig. 17 below), wherein the power transistor die (406) and the diode die assembly (408) are disposed on the first portion of the top metal layer [Fig. 17, ¶¶0046-0048].
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Regarding claim 11, Bayerer teaches the power semiconductor device arrangement of claim 10, further comprising a freewheeling diode (340, Fig. 13), wherein a cathode end (414C, Fig. 17) of the freewheeling diode is disposed on the first portion of the top metal layer, and wherein an anode end (424, Fig. 17) of the freewheeling diode is directly connected to the power semiconductor die [Fig. 13 and 17, ¶0051, Fig. 13 shows the freewheeling diode and Fig. 17 shows the configuration of the relationship of the cathode and anode in relation to the freewheeling diode and power semiconductor die].
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brayerer (US 20180233421 A1) and Morrish et al. (US 20150221630 A1).
Regarding claim 3, Brayerer teaches the power semiconductor device arrangement of claim 1, the diode die assembly comprising:
a first diode die (340), bonded to the top metal layer of the substrate (416) [Fig. 13 and 17, ¶¶0042 and 0047]; and
Bayerer doesn’t teach a transient voltage suppression.
Morrish et al. teaches a transient voltage suppression (TVS) diode die (622), disposed over the first diode die (620) [Fig. 6G, ¶0046].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the power semiconductor device as taught by Bayerer with the transient voltage suppression diode die as taught by Morrish et al. because a transient voltage suppression diode die would help protect the semiconductor device and allows for low resistance and Bayerer teaches a diodes on top of each other but doesn’t teach the top diode is a transient voltage suppression (TVS) diode die which is taught by Morrish et al.
Regarding claim 4, Bayerer in view of Morrish et al. teaches the power semiconductor device arrangement of claim 3, wherein a top surface of the TVS diode die (404) is connected to the first end of the wire bond connector (AC) [Fig. 17, ¶0050, figure shows the connection to wire bond].
Claim(s) 5, 6, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brayerer (US 20180233421 A1) in view of Morrish et al. (US 20150221630 A1) as applied to claim 3 above, further in view of Yao et al. (US 20170084601 A1).
Regarding claim 5, Bayerer in view of Morrish et al. teaches the power semiconductor device arrangement of claim 3.
Bayerer in view of Morrish et al. doesn’t teach the diodes in series and anode-to-anode configuration.
Yao et al. teaches a transient voltage suppressor with the TVS diode die (D1) and the first diode die (ZD) are electrically coupled in series to one another in an anode-to-anode configuration [Fig. 1A, ¶0019], wherein the first end of the wire bond connector is connected to a cathode of the TVS diode die [¶0023, bonding wires used to electrically connect different dice and would be electrically connected to a cathode of the die].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the display device as taught by Bayerer in view of Morrish et al. with the transient voltage suppressor configuration as taught by Yao et al. because the connection in series would allow for a positive conductive path which would allow for a low resistance route.
Regarding claim 6, Bayerer in view of Morrish et al. teaches the power semiconductor device arrangement of claim 3.
Bayerer in view of Morrish et al. doesn’t teach the diodes in series and cathode-to-cathode configuration.
Yao et al. teaches the TVS diode die (D11) and the first diode die (ZD) are electrically coupled in series to one another in a cathode-to-cathode configuration [Fig. 2, ¶0024], wherein the first end of the wire bond connector is connected to a cathode of the TVS diode die [¶0023, bonding wires used to electrically connect different dice and would be electrically connected to a cathode of the die].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the display device as taught by Bayerer in view of Morrish et al. with the transient voltage suppressor configuration as taught by Yao et al. because the connection in series would allow for a positive conductive path which would allow for a low resistance route.
Claim(s) 12, 13, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brayerer (US 20180233421 A1) in view of Yao et al. (US 20170084601 A1).
Regarding claim 12, Bayerer teaches a power semiconductor device module [¶0015], comprising:
a housing [¶0015, ]; and
a power semiconductor device arrangement [¶0007], comprising:
a substrate (400) [¶0007], the substrate comprising:
a ceramic body (418) [¶0055];
a top metal layer (416), disposed on a top surface of the ceramic body [Fig. 17, ¶0047]; and
a bottom metal layer (412), disposed on a bottom surface of the ceramic body, opposite the top surface [Fig. 17, ¶0047];
a power transistor die (402), comprising a power transistor device, the power transistor die being disposed over the top surface of the substrate [Fig. 17, ¶0046];
a diode die assembly (404), comprising a set of diodes, the diode die assembly disposed over the top surface of the substrate, adjacent to the power transistor die [Fig. 17, ¶0046].
The embodiment shown in Fig. 17 of Bayerer doesn’t show the wire bonding connecting the diode die assembly with the power transistor die.
The embodiment shown in Fig. 13 of Brayerer teaches a wire bond connector, having a first end, affixed to an upper surface of the diode die assembly (340), and a second end, affixed to an upper surface of the power transistor die (302) [Fig. 13, ¶¶0024 and 0042, talks about connection between dies and figure shows wire bonds attached to the dies].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the embodiments of Fig. 17 and Fig. 13 of Bayerer together to obtain the claimed display device because the device would have reverse blocking capability as taught by Fig. 13 with the inclusion of the diode die assembly and the power transistor die in the same packaging and Fig. 17 shows a sectional view of an embodiment that further illustrates the diode die assembly and power transistor die in the same packaging.
Bayerer doesn’t teach housing of a device module.
Yao et al. teaches a housing [¶0017].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the semiconductor package taught by Bayerer and the semiconductor device as taught by Yao et al. because the encapsulation to provide physical support and electrical isolation [¶0017, Yao et al.].
Regarding claim 13, Bayerer in view of Yao et al. teaches the power semiconductor device module of claim 12, the power transistor die comprising an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET) [¶0015].
Regarding claim 18, Bayerer in view of Yao et al. teaches the power semiconductor device module of claim 12, wherein the second end of the wire bond connector is affixed to a gate electrode (426, Fig. 17, Bayerer), the gate electrode being disposed on an upper surface of the power transistor die (406, Fig. 17) [Figs. 13 and 17, ¶¶0034 and 0042, Brayerer].
Regarding claim 19, Bayerer in view of Yao et al. and Morrish et al. teaches the power semiconductor device module of claim 16, wherein the power transistor die comprises a main terminal electrode (414, Fig. 17), disposed on a bottom surface of the power transistor die (406, Fig. 17), and wherein the main terminal electrode is bonded to the top metal layer of the substrate (416, Fig. 17) [¶¶0049-0050, Brayerer].
Regarding claim 20, Brayer in view of Yao et al. teaches the power semiconductor device arrangement of claim 12, the top metal layer comprising a first portion (as seen in Fig. 17 above, Brayerer), wherein the power transistor die (406) and the diode die assembly (408) are disposed on the first portion of the top metal layer [Fig. 17, ¶¶0046-0048, Brayerer].
Claim(s) 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brayerer (US 20180233421 A1) in view of Yao et al. (US 20170084601 A1) as applied to claim 12, further in view of Morrish et al. (US 20150221630 A1).
Regarding claim 14, Bayerer in view of Yao et al. teaches the power semiconductor device module of claim 12, the diode die assembly comprising:
a first diode die (340), bonded to the top metal layer of the substrate (416) [Fig. 13 and 17, ¶¶0042 and 0047, Bayerer]; and
Bayerer in view of Yao et al. doesn’t teach a transient voltage suppression.
Morrish et al. teaches a transient voltage suppression (TVS) diode die (622), disposed over the first diode die (620) [Fig. 6G, ¶0046].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the power semiconductor device as taught by Bayerer with the transient voltage suppression diode die as taught by Morrish et al. because a transient voltage suppression diode die would help protect the semiconductor device and allows for low resistance and Bayerer teaches a diodes on top of each other but doesn’t teach the top diode is a transient voltage suppression (TVS) diode die which is taught by Morrish et al.
Regarding claim 15, Bayerer in view of Yao et al. and Morrish et al. teaches the power semiconductor device module of claim 14, wherein a top surface of the TVS diode die (404) is connected to the first end of the wire bond connector (AC) [Fig. 17, ¶0050, figure shows the connection to wire bond, Bayerer].
Regarding claim 16, Bayerer in view of Yao et al. and Morrish et al. teaches the power semiconductor device module of claim 14, wherein the TVS diode die (D1) and the first diode die (ZD) are electrically coupled in series to one another in an anode-to-anode configuration [Fig. 1A, ¶0019, Yao et al.], wherein the first end of the wire bond connector is connected to a cathode of the TVS diode die [¶0023, bonding wires used to electrically connect different dice and would be electrically connected to a cathode of the die, Yao et al.].
Regarding claim 17, Bayerer in view of Yao et al. and Morrish et al. teaches the power semiconductor device module of claim 14, wherein the TVS diode die (D11) and the first diode die (ZD) are electrically coupled in series to one another in a cathode-to-cathode configuration [Fig. 2, ¶0024], wherein the first end of the wire bond connector is connected to a cathode of the TVS diode die [¶0023, bonding wires used to electrically connect different dice and would be electrically connected to a cathode of the die].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOOR MOHAMMAD ISMAIL TAHIR whose telephone number is (571)272-6166. The examiner can normally be reached Monday Friday, 8 a.m. 5 p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NOOR MOHAMMAD ISMAIL TAHIR/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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