DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 8.12.2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US 11038023 B2 and US 11942518 B2 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 186, 190-194, 196-197 and 199-201 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ishikura et al. (of record, US 20110233559 A1).
Regarding claim 186, Ishikura discloses a semiconductor structure (Figs. 1-2 and 5), comprising:
a substrate (11 or 41);
a III-nitride material region (12/13 or 42/43) located over the substrate;
a first-type electrode (22D and/or 21S; including 25s, 26Db and 26Da) over the III-nitride material region, the first-type electrode defining a first electrode interfacial (including less than a total interface area per MPEP 2111) area (seen in Fig. 2) with the III-nitride material region; and
a second-type electrode (23G) over the III-nitride material region, the second-type electrode defining a second electrode interfacial (including up to a total interface area per MPEP 2111) area (seen in Fig. 2) with the III-nitride material region, wherein
the first electrode interfacial area is less than 50 times the second electrode interfacial area (Fig. 2, MPEP 2111 and 2125; while Ishikura discloses “the scales and positions of the elements shown in the figures are different from their actual scales and positions”, the examiner notes that that MPEP 2125 states “Drawings and pictures can anticipate claims if they clearly show the structure which is claimed” and in the instant case since the claim does limit the claimed interfacial areas to comprise an entirety of the interface between the electrodes and the III-nitride material region, per MPEP 2111, the claimed interfacial areas includes partial areas thereof, and per MPEP 2125, there are user-defined partial areas which meet the claimed limitations based on relative sizing of portions of the electrodes even if the electrodes are not to scale because the user-defined partial areas still meet the claimed limitations and because the first and the second electrodes must comprise interfacial areas as claimed).
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Regarding claim 190, Ishikura discloses the semiconductor structure of claim 186, wherein:
the first-type electrode (22D and/or 21S) comprises drain and source ohmic contacts (“drain ohmic contacts 26Da and 26Db” and “source ohmic contact 25S”) of a transistor;
the first electrode interfacial area (Fig. 2 above) comprises a sum of (including partial areas per MPEP 211) interfacial areas of the drain and source ohmic contacts (Fig. 2 above) with the III-nitride material region; and
the second-type electrode comprises a gate contact (“gate electrode 23G”) of the transistor.
Regarding claims 191-193, Ishikura discloses (claim 191) the semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 40 times the second electrode interfacial area, (claim 192) the semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 30 times the second electrode interfacial area, and (claim 193) the semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 20 times the second electrode interfacial area (Fig. 2, MPEP 2111 and 2125; while Ishikura discloses “the scales and positions of the elements shown in the figures are different from their actual scales and positions”, the examiner notes that that MPEP 2125 states “Drawings and pictures can anticipate claims if they clearly show the structure which is claimed” and in the instant case since the claim does limit the claimed interfacial areas to comprise an entirety of the interface between the electrodes and the III-nitride material region, per MPEP 2111, the claimed interfacial areas includes partial areas thereof, and per MPEP 2125, there are user-defined partial areas which meet the claimed limitations based on relative sizing of portions of the electrodes even if the electrodes are not to scale because the user-defined partial areas still meet the claimed limitations and because the first and the second electrodes must comprise interfacial areas as claimed).
Regarding claim 194, Ishikura discloses the semiconductor structure of claim 186, further comprising an active area (Fig. 2 below; MPEP 2111 and 2125) under and (partly) between (and extending beyond) the first-type electrode and the second-type electrode, wherein a sum of the first electrode interfacial area and the second electrode interfacial area is less than 30% of the active area (Fig. 2, the active area is under/between/beyond the first-type electrode and the second-type electrode, which is not precluded by the claim, so that a sum of the first electrode interfacial area and the second electrode interfacial area is less than 30% of the active area per MPEP 2111 and 2125 because the active area is significantly greater in relative sizing than the user-defined partial areas of the interfacial areas even if the electrodes are not to scale because the active area surrounds an entirety of the device and the interfacial areas are user-defined minute partial areas).
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Regarding claim 196, Ishikura discloses the semiconductor structure of claim 186, further comprising:
an active area under and between the first-type electrode and the second-type electrode (Fig. 2 above, the active area is under/between/beyond the first-type electrode and the second-type electrode which is not precluded by the claim), wherein:
the first-type electrode comprises drain and source ohmic contacts of a transistor (“drain ohmic contacts 26Da and 26Db” and “source ohmic contact 25S”);
the first electrode interfacial area comprises first interfacial areas of the drain and source ohmic contacts with the III-nitride material region (Fig. 2 above);
the second-type electrode comprises a gate contact (“gate electrode 23G”) of the transistor;
the second electrode interfacial area comprises an interfacial area of the gate contact with the IIII-nitride material region (Fig. 2 above); and
a sum of the interfacial areas of the drain and source ohmic contacts and the interfacial area of the gate contact is less than 30% of the active area of the IIII-nitride material region under and (partly) between (and beyond) the drain and source ohmic contacts and the gate contact (Fig. 2, the active area is under/between/beyond the first-type electrode and the second-type electrode, which is not precluded by the claim, so that a sum of the interfacial areas of the drain and source ohmic contacts and the interfacial area of the gate contact is less than 30% of the active area per MPEP 2111 and 2125 because the active area is significantly greater in relative sizing than the user-defined partial areas of the interfacial areas even if the electrodes are not to scale because the active area surrounds an entirety of the device and the interfacial areas are user-defined minute partial areas).
Regarding claim 197, Ishikura discloses the semiconductor structure of claim 186, wherein at least a portion of the substrate has an electronic resistivity of less than 0.10 Ω-cm at 25 °C ([0056] for room temperature which is assumed to be 25C and [0086] for resistivity).
Regarding claim 199, Ishikura discloses the semiconductor structure of claim 186, wherein at least a portion of the substrate comprises silicon ([0056], [0086]).
Regarding claim 200, Ishikura discloses the semiconductor structure of claim 186, wherein at least a portion of the substrate comprises silicon carbide ([0101]).
Regarding claim 201, Ishikura discloses the semiconductor structure of claim 186, wherein the III-nitride material region comprises gallium nitride materials ([0086]).
Claims 187-188 and 198 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikura et al. (of record, US 20110233559 A1).
Regarding claims 187 and 188, Ishikura discloses (claim 187) the semiconductor structure of claim 186, wherein the first-type electrode comprises an ohmic contact (“drain ohmic contacts 26Da and 26Db” and “source ohmic contact 25S”) and (claim 188) the semiconductor structure of claim 186, wherein the first-type electrode comprises an ohmic contact (“drain ohmic contacts 26Da and 26Db” and “source ohmic contact 25S”).
Ishikura fails to disclose (claim 187) the second-type electrode comprises a Schottky contact and (claim 188) the second-type electrode comprises a capacitive contact.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at a Schottky or capacitive contact because said type of contacts are well-known and commonplace in the semiconductor arts, their use was within the skill set of one of ordinary skill in the art, and their use would have yielded predictable results such as forming a diode or a transistor.
Regarding claim 198, Ishikura fails to disclose the semiconductor structure of claim 186, wherein at least a portion of the substrate has an electronic resistivity of 10,000 Ω-cm at 25 °C.
Ishikura discloses “the substrate 11 is a p-type high-resistivity Si substrate with a resistivity of 2.0x103 Ωcm at room temperature” ([0056]. 25C is considered room temperature).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive the claimed resistivity because such a substrate is well-known and commonplace in the semiconductor arts, their use was within the skill set of one of ordinary skill in the art, and their use would have yielded predictable results such as forming a diode or a transistor.
Claims 202-205 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikura et al. (of record, US 20110233559 A1) in view of Roberts et al. (of record, US 9627473 B2).
Regarding claim 202, Ishikura fails to disclose the semiconductor structure of claim 186, wherein the III-nitride material region comprises: a nucleation layer over the substrate; a buffer layer over the nucleation layer; and a device region over the buffer layer.
Roberts discloses wherein the III-nitride material region (120) comprises: a nucleation layer (155) over the substrate; a buffer layer (180) over the nucleation layer; and a device region (190) over the buffer layer (Fig. 1D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the layers of Roberts in Ishikura so as to facilitate and prepare surfaces of a substrate from subsequent layer growth per Roberts (e.g., “prepare a surface of the substrate for growth of III-nitride material” and “provide a surface for the growth of epitaxial III-nitride material above the buffer layer”).
Regarding claim 203, Ishikura/Roberts discloses the semiconductor structure of claim 202, further comprising a transition layer (170) located between the nucleation layer (155) and the buffer layer (180).
Regarding claims 204 and 205, Ishikura/Roberts discloses (claim 204) the semiconductor structure of claim 203, wherein the transition layer comprises a superlattice (“the transition layer may be made of, at least in part, one or more superlattices (including strained layer superlattices (SLS) or multiple quantum wells (MQW)) and/or a compositionally-graded superlattice or compositionally graded MQW”) and (claim 205) the semiconductor structure of claim 203, wherein the transition layer is compositionally graded (“the transition layer may be made of, at least in part, one or more superlattices (including strained layer superlattices (SLS) or multiple quantum wells (MQW)) and/or a compositionally-graded superlattice or compositionally graded MQW”)
Allowable Subject Matter
Claims 189 and 195 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 189, the prior art of record fails to disclose or suggest the semiconductor structure of claim 186, wherein: the first-type electrode comprises a cathode of a diode; and the second-type electrode comprises an anode of the diode.
Regarding claim 195, the prior art of record fails to disclose or suggest the first-type electrode comprises a cathode of a diode; the second-type electrode comprises an anode of the diode; and a sum of the first electrode interfacial area of the cathode and the second electrode interfacial area of the anode is less than 60% of the active area of the III-nitride material region under and between the cathode and the anode.
Response to Arguments
Applicant's arguments filed 8.12.2026 have been fully considered but they are not persuasive. The applicant alleges:
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This not found entirely persuasive because while Ishikura discloses “the scales and positions of the elements shown in the figures are different from their actual scales and positions”, the examiner notes that that MPEP 2125 states “Drawings and pictures can anticipate claims if they clearly show the structure which is claimed” and in the instant case since the claim does limit the claimed interfacial areas to comprise an entirety of the interface between the electrodes and the III-nitride material region, per MPEP 2111, the claimed interfacial areas include partial areas thereof, and per MPEP 2125, there are user-defined partial areas which meet the claimed limitations based on relative sizing of portions of the electrodes even if the electrodes are not to scale because the user-defined partial areas still meet the claimed limitations and because the first and the second electrodes must comprise interfacial areas as claimed.
A non-final rejection is being issued since the examiner modified the rejection rationale for claim 186.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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