DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The listing of references in the specification is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 191-193 and 196 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 191-193, “The semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 30 times the second electrode interfacial area” (claim 191), “The semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 40 times the second electrode interfacial area” (claim 192) and “The semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 50 times the second electrode interfacial area” (claim 193) are indefinite as the ranges claimed contradict the pre-requisite requirement of “the first electrode interfacial area is less than 20 times the second electrode interfacial area” of base claim 186.
That is, claims 191-193 recite ranges which are outside of the pre-requisite range of base claim 186 and this renders the claims indefinite. Claims are treated as presented or as requiring an area relationship of less than 20 times per base claim 186.
Regarding claim 196, “the (replace with “a”?) sum of the (insert –first--?) interfacial areas of the drain and source ohmic contacts“ lack proper antecedent basis. Treated as suggested in parentheses.
Claims 191-193 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding claims 191-193, “The semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 30 times the second electrode interfacial area” (claim 191), “The semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 40 times the second electrode interfacial area” (claim 192) and “The semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 50 times the second electrode interfacial area” (claim 193) fail to include all the limitations of base claim 186 as the ranges claimed include values outside of the pre-requisite requirement of “the first electrode interfacial area is less than 20 times the second electrode interfacial area” of base claim 186.
That is, claims 191-193 recite ranges which are outside of the pre-requisite range of base claim 186 and the claims fail to include all the limitations of base claim 186. Claims are treated as presented or as requiring an area relationship of less than 20 times per base claim 186.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 186-188, 191-193, 197 and 199-205 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 6-10 of U.S. Patent No. 11038023 B2.
Although the claims at issue are not identical, they are not patentably distinct from each other because they substantially overlap in scope such that the claims of U.S. Patent No. 11038023 B2 anticipate or render obvious claims of the instant application.
Regarding claim 186, claim 1 of U.S. Patent No. 11038023 B2 discloses all the positively recited limitations of claim 186 except for “the first electrode interfacial area is less than 20 times the second electrode interfacial area” wherein claim 1 of U.S. Patent No. 11038023 B2 discloses a different range as “wherein the ohmic contact interfacial area is less than 50 times the gate electrode interfacial area”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at a value within both the claimed range and that of the reference application because “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists” per MPEP 2144.05 and/or so as to minimize the size of electrodes within a diode or transistor device and thereby enable higher device density and integration.
Regarding claim 187-188, claim 1 of U.S. Patent No. 11038023 B2 discloses the first-type electrode comprises an ohmic contact but fails to disclose “the second-type electrode comprises a Schottky contact” (claim 187) and “the second-type electrode comprises a capacitive contact” (claim 188).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at a Schottky or capacitive contact because said type of contacts are well-known and commonplace in the semiconductor arts, their use was within the skill set of one of ordinary skill in the art, and their use would have yielded predictable results such as forming a diode or a transistor.
Regarding claims 191-192, claim 1 of U.S. Patent No. 11038023 B2 does not disclose “wherein the first electrode interfacial area is less than 30 times the second electrode interfacial area” (claim 191) and “wherein the first electrode interfacial area is less than 40 times the second electrode interfacial area” (claim 192) wherein claim 1 of U.S. Patent No. 11038023 B2 discloses a different range as “wherein the ohmic contact interfacial area is less than 50 times the gate electrode interfacial area”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at a value within both the claimed ranges and that of the reference application because “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists” per MPEP 2144.05 and/or so as to minimize the size of electrodes within a diode or transistor device and thereby enable higher device density and integration.
Regarding claim 193, claim 1 of U.S. Patent No. 11038023 B2 discloses the claim.
Regarding claim 197, claim 1 of U.S. Patent No. 11038023 B2 discloses the claim.
Regarding claim 199, claim 1 of U.S. Patent No. 11038023 B2 discloses the claim.
Regarding claim 200, claim 1 of U.S. Patent No. 11038023 B2 does not disclose “silicon carbide”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ SiC because said substrate material is well-known and commonplace in the semiconductor arts, their use was within the skill set of one of ordinary skill in the art, and their use would have yielded predictable results such as forming a bases for a high-power device.
Regarding claim 201, claim 6 of U.S. Patent No. 11038023 B2 discloses the claim.
Regarding claim 202, claim 7 of U.S. Patent No. 11038023 B2 discloses the claim.
Regarding claim 203, claim 8 of U.S. Patent No. 11038023 B2 discloses the claim.
Regarding claim 204, claim 9 of U.S. Patent No. 11038023 B2 discloses the claim.
Regarding claim 205, claim 10 of U.S. Patent No. 11038023 B2 discloses the claim.
Claims 186-188, 191-193 and 197-205 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 8-12 and 15-17 of U.S. Patent No. 11942518 B2.
Although the claims at issue are not identical, they are not patentably distinct from each other because they substantially overlap in scope such that the claims of U.S. Patent No. 11942518 B2 anticipate or render obvious claims of the instant application.
Regarding claim 186, claim 1 of U.S. Patent No. 11942518 B2 discloses all the positively recited limitations of claim 186 except for “the first electrode interfacial area is less than 20 times the second electrode interfacial area” wherein claim 1 of U.S. Patent No. 11942518 B2 discloses a different range as “wherein the ohmic contact interfacial area is less than 50 times the gate electrode interfacial area”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at a value within both the claimed range and that of the reference application because “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists” per MPEP 2144.05 and/or so as to minimize the size of electrodes within a diode or transistor device and thereby enable higher device density and integration.
Regarding claim 187-188, claim 1 of U.S. Patent No. 11942518 B2 discloses the first-type electrode comprises an ohmic contact but fails to disclose “the second-type electrode comprises a Schottky contact” (claim 187) and “the second-type electrode comprises a capacitive contact” (claim 188).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at a Schottky or capacitive contact because said type of contacts are well-known and commonplace in the semiconductor arts, their use was within the skill set of one of ordinary skill in the art, and their use would have yielded predictable results such as forming a diode or a transistor.
Regarding claims 191, claims 15 and 17 of U.S. Patent No. 11942518 B2 disclose the claim.
Regarding claims 192, claims 15 and 16 of U.S. Patent No. 11942518 B2 disclose the claim.
Regarding claim 193, claim 1 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 197, claim 2 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 198, claim 3 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 199, claim 4 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 200, claim 5 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 201, claim 8 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 202, claim 9 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 203, claim 10 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 204, claim 11 of U.S. Patent No. 11942518 B2 discloses the claim.
Regarding claim 205, claim 12 of U.S. Patent No. 11942518 B2 discloses the claim.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 186, 190-194, 196-197 and 199-201 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ishikura et al. (US 20110233559 A1).
Regarding claim 186, Ishikura discloses a semiconductor structure (Figs. 1-2 and 5), comprising:
a substrate (11 or 41);
a III-nitride material region (12/13 or 42/43) located over the substrate;
a first-type electrode (22D and/or 21S) over the III-nitride material region, the first-type electrode defining a first electrode interfacial (including less than a total interface area per MPEP 2111) area (seen in Fig. 2) with the III-nitride material region; and
a second-type electrode (23G) over the III-nitride material region, the second-type electrode defining a second electrode interfacial area (seen in Fig. 2) with the III-nitride material region, wherein
the first electrode interfacial area is less than 20 times the second electrode interfacial area (Fig. 2, MPEP 2111 and 2125; the highlighted sections of 22D and/or 21S are less than 20 times the highlighted section of 23G since 22Da is approximately the same size of 23G and the partial area highlighted of 21S is less than that of 23G).
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Regarding claim 190, Ishikura discloses the semiconductor structure of claim 186, wherein:
the first-type electrode (22D and/or 21S) comprises drain and source ohmic contacts (“drain ohmic contacts 26Da and 26Db” and “source ohmic contact 25S”) of a transistor;
the first electrode interfacial area (Fig. 2 above) comprises a sum of (including partial areas per MPEP 211) interfacial areas of the drain and source ohmic contacts (Fig. 2 above) with the III-nitride material region; and
the second-type electrode comprises a gate contact (“gate electrode 23G”) of the transistor.
Regarding claims 191-193, Ishikura discloses (claim 191) the semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 30 times the second electrode interfacial area, (claim 192) the semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 40 times the second electrode interfacial area, and (claim 193) the semiconductor structure of claim 186, wherein the first electrode interfacial area is less than 50 times the second electrode interfacial area (Fig. 2 above, MPEP 2111 and 2125; the highlighted sections of 22D and/or 21S are less than 30/40/50 times the highlighted section of 23G since 22Da is approximately the same size of 23G and the partial area highlighted of 21S is less than that of 23G).
Regarding claim 194, Ishikura discloses the semiconductor structure of claim 186, further comprising an active area (Fig. 2 below; MPEP 2111 and 2125) under and (partly) between (and extending beyond) the first-type electrode and the second-type electrode, wherein a sum of the first electrode interfacial area and the second electrode interfacial area is less than 30% of the active area (Fig. 2, the active area is under/between/beyond the first-type electrode and the second-type electrode so that a sum of the first electrode interfacial area and the second electrode interfacial area is less than 30% of the active area per MPEP 2111 and 2125).
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Regarding claim 196, Ishikura discloses the semiconductor structure of claim 194, wherein:
the first-type electrode comprises drain and source ohmic contacts of a transistor (“drain ohmic contacts 26Da and 26Db” and “source ohmic contact 25S”);
the first electrode interfacial area comprises first interfacial areas of the drain and source ohmic contacts with the III-nitride material region (Fig. 2 above);
the second-type electrode comprises a gate contact (“gate electrode 23G”) of the transistor;
the second electrode interfacial area comprises an interfacial area of the gate contact with the IIII-nitride material region (Fig. 2 above); and
the sum of the interfacial areas of the drain and source ohmic contacts and the interfacial area of the gate contact is less than 30% of the active area of the IIII-nitride material region under and (partly) between (and beyond) the drain and source ohmic contacts and the gate contact (Fig. 2, the active area is under/between/beyond the drain and source ohmic contacts so that the sum of the interfacial areas of the drain and source ohmic contacts and the interfacial area of the gate contact is less than 30% of the active area per MPEP 2111 and 2125).
Regarding claim 197, Ishikura discloses the semiconductor structure of claim 186, wherein at least a portion of the substrate has an electronic resistivity of less than 0.10 Ω-cm at 25 °C ([0056] for room temperature which is assumed to be 25C and [0086] for resistivity).
Regarding claim 199, Ishikura discloses the semiconductor structure of claim 186, wherein at least a portion of the substrate comprises silicon ([0056], [0086]).
Regarding claim 200, Ishikura discloses the semiconductor structure of claim 186, wherein at least a portion of the substrate comprises silicon carbide ([0101]).
Regarding claim 201, Ishikura discloses the semiconductor structure of claim 186, wherein the III-nitride material region comprises gallium nitride materials ([0086]).
Claims 187-188 and 198 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikura et al. (US 20110233559 A1).
Regarding claims 187 and 188, Ishikura discloses (claim 187) the semiconductor structure of claim 186, wherein the first-type electrode comprises an ohmic contact (“drain ohmic contacts 26Da and 26Db” and “source ohmic contact 25S”) and (claim 188) the semiconductor structure of claim 186, wherein the first-type electrode comprises an ohmic contact (“drain ohmic contacts 26Da and 26Db” and “source ohmic contact 25S”).
Ishikura fails to disclose (claim 187) the second-type electrode comprises a Schottky contact and (claim 188) the second-type electrode comprises a capacitive contact.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at a Schottky or capacitive contact because said type of contacts are well-known and commonplace in the semiconductor arts, their use was within the skill set of one of ordinary skill in the art, and their use would have yielded predictable results such as forming a diode or a transistor.
Regarding claim 198, Ishikura fails to disclose the semiconductor structure of claim 186, wherein at least a portion of the substrate has an electronic resistivity of 10,000 Ω-cm at 25 °C.
Ishikura discloses “the substrate 11 is a p-type high-resistivity Si substrate with a resistivity of 2.0x103 Ωcm at room temperature” ([0056]. 25C is considered room temperature).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive the claimed resistivity because such a substrate is well-known and commonplace in the semiconductor arts, their use was within the skill set of one of ordinary skill in the art, and their use would have yielded predictable results such as forming a diode or a transistor.
Claims 202-205 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikura et al. (US 20110233559 A1) in view of Roberts et al. (US 9627473 B2).
Regarding claim 202, Ishikura fails to disclose the semiconductor structure of claim 186, wherein the III-nitride material region comprises: a nucleation layer over the substrate; a buffer layer over the nucleation layer; and a device region over the buffer layer.
Roberts discloses wherein the III-nitride material region (120) comprises: a nucleation layer (155) over the substrate; a buffer layer (180) over the nucleation layer; and a device region (190) over the buffer layer (Fig. 1D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the layers of Roberts in Ishikura so as to facilitate and prepare surfaces of a substrate from subsequent layer growth per Roberts (e.g., “prepare a surface of the substrate for growth of III-nitride material” and “provide a surface for the growth of epitaxial III-nitride material above the buffer layer”).
Regarding claim 203, Ishikura/Roberts discloses the semiconductor structure of claim 202, further comprising a transition layer (170) located between the nucleation layer (155) and the buffer layer (180).
Regarding claims 204 and 205, Ishikura/Roberts discloses (claim 204) the semiconductor structure of claim 203, wherein the transition layer comprises a superlattice (“the transition layer may be made of, at least in part, one or more superlattices (including strained layer superlattices (SLS) or multiple quantum wells (MQW)) and/or a compositionally-graded superlattice or compositionally graded MQW”) and (claim 205) the semiconductor structure of claim 203, wherein the transition layer is compositionally graded (“the transition layer may be made of, at least in part, one or more superlattices (including strained layer superlattices (SLS) or multiple quantum wells (MQW)) and/or a compositionally-graded superlattice or compositionally graded MQW”)
Allowable Subject Matter
Claims 189 and 195 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 189, the prior art of record fails to disclose or suggest the semiconductor structure of claim 186, wherein: the first-type electrode comprises a cathode of a diode; the second-type electrode comprises an anode of the diode.
Regarding claim 195, the prior art of record fails to disclose or suggest the first-type electrode comprises a cathode of a diode; the second-type electrode comprises an anode of the diode; and a sum of the first electrode interfacial area of the cathode and the second electrode interfacial area of the anode is less than 30% of the active area of the III-nitride material region under and between the cathode and the anode.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8618578 B2 to Ota et al. discloses (Fig. 1) a substrate (101), nitride-based semiconductor layers (102-107), a first electrode (108/109) and a second electrode (112).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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