DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11948973 (hereinafter `973) in view of JAMBUNATHAN et al. (US 20190355721).
Regarding claim 1, `973 discloses all the limitation, fails to teach that forming dielectric fins on the isolation regions, wherein the dielectric fins comprise a first dielectric layer and a first dielectric liner material around the first dielectric layer; and forming dielectric structures on the dielectric fins, wherein the dielectric structures comprise a second dielectric layer and a second dielectric liner material around the second dielectric layer, wherein the dielectric fins and the dielectric structures form the hybrid fins.
However, JAMBUNATHAN teaches that forming dielectric fins 230 on the isolation regions 220, wherein the dielectric fins 230 (para. 0037) comprise a first dielectric layer 230 and a first dielectric liner material (para. 0037, note:” a multilayer structure “) around the first dielectric layer 230; and forming dielectric structures 270 on the dielectric fins, wherein the dielectric structures comprise a second dielectric layer and a second dielectric liner material around the second dielectric layer (para. 0060), wherein the dielectric fins and the dielectric structures form the hybrid fins 230 & 270 (Fig. 2N).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide `973 with forming dielectric fins on the isolation regions, wherein the dielectric fins comprise a first dielectric layer and a first dielectric liner material around the first dielectric layer; and forming dielectric structures on the dielectric fins, wherein the dielectric structures comprise a second dielectric layer and a second dielectric liner material around the second dielectric layer, wherein the dielectric fins and the dielectric structures form the hybrid fins as taught by JAMBUNATHAN in order to improve device performance (par. 0050) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 9, `973 & JAMBUNATHAN discloses that all of limitations including the dielectric structure 230 extends further from the substrate 200 than the gate structure 244, wherein the gate structure extends along sidewalls of the first portion of the first dielectric fin and along a first upper surface of the first portion of the first dielectric fin distal from the substrate, wherein the gate structure extends along a first sidewall of the first portion of the second dielectric fin, but not along a second upper surface of the first portion of the second dielectric fin distal from the substrate (Fig. 2E-2H).
Reclaim 17, `973 & JAMBUNATHAN discloses that all of limitations including a gate dielectric material 250 & 242 of the gate structure extends along an upper surface of the first dielectric fin 230 distal from the substrate, wherein the upper surface of the second dielectric fin is free of the gate dielectric material (Fig. 2E-2F. note: other sides of dielectric fin is free of the gate dielectric material and center surface).
Conclusion
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/SU C KIM/ Primary Examiner, Art Unit 2899
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