Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 6/29/2026. Applicant has elected Species D, corresponding to Figs. 19A-19D. The non-elected species, corresponding to the other figures described in the requirement, are withdrawn from further consideration.
The examiner acknowledges the applicant’s cancellation of claim 17.
The examiner also acknowledges new claim 21.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5-6, 9-10, 12-13, 15-16, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-447 (US # 20150162447) in view of Lee-556 (US # 9570556).
Regarding Claim 1, Lee-447 teaches a semiconductor device (see Fig. 1 and corresponding text), comprising:
an isolation insulating layer (20) disposed over a substrate (12);
a semiconductor fin (40) disposed over the substrate, an upper portion (strained region16) of the semiconductor fin protruding from the isolation insulating layer and a lower portion (14) of the semiconductor fin being embedded in the isolation insulating layer (see Fig. 1), the upper portion of the semiconductor fin comprising an upper epitaxial growth enhancement layer (SiGe alloy layer 28), and the lower portion of the semiconductor fin comprising a lower epitaxial growth enhancement layer (26) disposed below an upper surface (level with the lowest surface of feature 16) of the isolation insulating layer (shown);
a gate structure (see [0020]) disposed over the upper portion of the semiconductor fin including the upper epitaxial growth enhancement layer, the gate structure including a gate dielectric layer and a gate electrode layer (described in [0020-21]);
gate sidewall spacers (32; see Fig. 2) disposed over opposing side faces of the gate structure (shown); and
a source/drain contacts (30) in contact with the upper epitaxial growth enhancement layer ([0022]).
Although Lee-447 discloses much of the claimed invention, it does not explicitly teach the device wherein each of the source/drain structures includes a source/drain epitaxial layer.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Lee-556 is in the same or analogous field, and it teaches a device (see Fig. 7) wherein each of the source/drain structures includes a source/drain epitaxial layer (60; see Figs. 9-10 and corresponding text) which contact an upper portion of a fin (20), the upper portion protruding above an isolation feature (30).
A person having ordinary skill in the art would have recognized that modifying the S/D features of Lee-447 with the epitaxial details suggested by Lee-556 would be obvious. Specifically, the modification suggested by Lee-556 would be to employ a device wherein each of the source/drain structures includes a source/drain epitaxial layer. The rationale for this obvious modification is that source/drain epitaxial layer provides lower resistance.
Regarding Claim 2, Lee-447 teaches the semiconductor device of claim 1, wherein the upper epitaxial growth enhancement layer includes one of SiP, SiCP, SiGe and SiGeB ([0019, 26]).
Regarding Claim 5, Lee-447 teaches the semiconductor device of claim 1, wherein the upper epitaxial growth enhancement layer is located at spaced from a top of the semiconductor fin ([0016, 18, 26]).
Regarding Claim 6, Lee-447 teaches the semiconductor device of claim 5, wherein a composition of the upper epitaxial growth enhancement layer is different from a composition of the lower epitaxial growth enhancement layer (see rejection of claim 5).
Regarding Claim 9, Lee-447 teaches a semiconductor device, comprising:
an isolation insulating layer (20) disposed over a substrate (12);
a semiconductor fin disposed over the substrate and including a bottom fin layer (22), one or more body layers, and a plurality of epitaxial growth enhancement layers made of different material than the one or more body layers (other features map the same way as claim 1);
an embedded epitaxial growth enhancement layer of the plurality of epitaxial growth enhancement layers being below an upper surface of the isolation insulating layer (other features map the same way as claim 1);
a protruding epitaxial growth enhancement layer of the plurality of epitaxial growth enhancement layers being present in a portion of the semiconductor fin protruding outside the isolation insulating layer (map the same way as claim 1);
a gate structure disposed over a channel region of the semiconductor fin and including a gate dielectric layer and a gate electrode layer; [[and]] gate sidewall spacers disposed over opposing side faces of the gate structure (map the same way as claim 1); and
a source/drain contacts (30) in contact with the upper epitaxial growth enhancement layer (map the same way as claim 1).
The combination of Lee-556 is the same as claim 1, to make a prima facie case that claim 9 is obvious.
Regarding Claim 10, Lee-447 teaches the semiconductor device of claim 9, wherein at least one of the plurality of epitaxial growth enhancement layers is made of one of SiP, SiGe, SiGeB and SiCP (see the rejection of claim 2).
Regarding Claim 12, Lee-447 in view of Lee-556, as applied to claim 9, teaches the semiconductor device of claim 9, wherein the embedded epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer (see rejection of claim 9).
Regarding Claim 13, Lee-447 teaches the semiconductor device of claim 9, further comprising an intermediate epitaxial growth enhancement layer (24) of the plurality of epitaxial growth enhancement layers, the intermediate epitaxial growth enhancement layer being between the embedded and protruding epitaxial growth enhancement layers in the semiconductor fin (between the lowest 24 and the strained layer 16).
Regarding Claim 15, although Lee-447 in view of Lee-556 discloses much of the claimed invention, it does not explicitly teach the semiconductor device of claim 9, wherein the protruding epitaxial growth enhancement layer has a non-uniform composition.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
Lee-447 teaches a Ge gradient in the SiGe epitaxy, for producing strain ([0004, 28]), which is useful for the stressed gate channel 36. Thus it would have been obvious.
Regarding Claim 16, although Lee-447 in view of Lee-556 discloses much of the claimed invention, it does not explicitly teach the semiconductor device of claim 12, wherein the embedded epitaxial growth enhancement layer has a non-uniform composition.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
Lee-447 teaches a Ge gradient in the SiGe epitaxy, for producing strain ([0004, 28]), which is useful for the stressed gate channel 36. Thus it would have been obvious.
Regarding Claim 18, Lee-447 teaches a semiconductor device, comprising:
a semiconductor fin (40) disposed over a substrate (12), a first portion (16) of the semiconductor fin comprising a protruding epitaxial growth enhancement layer (16), and a second portion (24) of the semiconductor fin comprising an embedded epitaxial growth enhancement layer (24 is embedded in 20);
an isolation insulating layer (20), the first portion of the semiconductor fin protruding from the isolation insulating layer, and the second portion of the semiconductor fin being embedded in the isolation insulating layer with the embedded epitaxial growth enhancement layer below an upper surface of the isolation insulating layer (shown);
a gate structure (18) disposed over the first portion of the semiconductor fin; and
a source/drain contacts
Lee-556 renders this difference obvious for the same reasons as in claims 1 and 9.
Regarding Claim 19, Lee-447 teaches the semiconductor device of claim 18, wherein the source/drain epitaxial layer contacts the embedded epitaxial growth enhancement layer (same reasons as claim 12).
Regarding Claim 20, Lee-447 teaches the semiconductor device of claim 18, wherein a composition of the embedded epitaxial growth enhancement layer is different from a composition of the protruding epitaxial growth enhancement layer (same reasons as claim 6).
Regarding Claim 21, Lee-447 teaches the semiconductor device of claim 18, wherein the semiconductor fin further includes an intermediate epitaxial growth enhancement layer between the protruding epitaxial growth enhancement layer and the embedded epitaxial growth enhancement layer (same reasons as claim 13).
Claims 3, 7, 8, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-447 (US # 20150162447) in view of Lee-556 (US # 9570556) and further in view of Chi (US # 20150228648).
Regarding Claim 3, although Lee-447 in view of Lee-556 discloses much of the claimed invention, it does not explicitly teach the semiconductor device of claim 1, wherein the upper epitaxial growth enhancement layer is located at spaced from a top of the semiconductor fin.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Chi is in the same or analogous field, and it teaches a semiconductor device (see Figs. 2 and corresponding text) wherein an upper epitaxial growth enhancement layer (209) is located at spaced from a top of a semiconductor fin (top of layer 211).
A person having ordinary skill in the art would have recognized that modifying the strained layer of Lee-447 in view of Lee-556 with the epitaxial multi-layer layer suggested by Chi would be obvious. Specifically, the modification suggested by Chi would be to employ a semiconductor device of claim 1, wherein the upper epitaxial growth enhancement layer is located at spaced from a top of the semiconductor fin. The rationale for this obvious modification is that the Chi multi-layer stack provides multi-value logic ([0019, 35]) in a single-fin footprint.
Regarding Claim 7, although Lee-447 in view of Lee-556 discloses much of the claimed invention, it does not explicitly teach the semiconductor device of claim 5, wherein the upper portion of the semiconductor fin further includes a third epitaxial growth enhancement layer made of a semiconductor material different from the remaining part of the semiconductor fin other than the upper and lower epitaxial growth enhancement layers.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Chi is in the same or analogous field, and it teaches a semiconductor device (see Figs. 2 and corresponding text) including an upper portion of a semiconductor fin (three-layer stacked Si-based layers of different composition 207, 209, 211), wherein the upper portion of the semiconductor fin further includes a third epitaxial growth enhancement layer (207) made of a semiconductor material different from the remaining part (SiGe alloys are different from Si-only feature 201) of the semiconductor fin other than the upper and lower epitaxial growth enhancement layers (shown; [0022-23]).
A person having ordinary skill in the art would have recognized that modifying the strained layer of Lee-447 in view of Lee-556 with the epitaxial multi-layer layer suggested by Chi would be obvious. Specifically, the modification suggested by Chi would be to employ a semiconductor device of claim 5, wherein the upper portion of the semiconductor fin further includes a third epitaxial growth enhancement layer made of a semiconductor material different from the remaining part of the semiconductor fin other than the upper and lower epitaxial growth enhancement layers. The rationale for this obvious modification is that the Chi multi-layer stack provides multi-value logic ([0019, 35]) in a single-fin footprint.
Regarding Claim 8, Chi, as applied to claim 7, teaches semiconductor device of claim 7, wherein a composition of the third epitaxial growth enhancement layer is different from compositions of the upper and lower epitaxial growth enhancement layers.
Regarding Claim 14, although Lee-447 in view of Lee-556 discloses much of the claimed invention, it does not explicitly teach the semiconductor device of claim 13, wherein the intermediate epitaxial growth enhancement layer is present in a portion of the semiconductor fin protruding outside the isolation insulating layer, and the gate dielectric layer covers the protruding and intermediate epitaxial growth enhancement layers.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Chi is in the same or analogous field, and it teaches a semiconductor device (see Figs. 2 and corresponding text) including an upper portion of a semiconductor fin (three-layer stacked Si-based layers of different composition 207, 209, 211), wherein an intermediate epitaxial growth enhancement layer (209) is present in a portion of the semiconductor fin protruding outside the isolation insulating layer, and the gate dielectric layer ([0022] describes a gate dielectric under gate electrode 213) covers the protruding and intermediate epitaxial growth enhancement layers (shown in Figs. 2).
A person having ordinary skill in the art would have recognized that modifying the protruding portion of Lee-447 in view of Lee-556 with the epitaxial multi-layer layer suggested by Chi would be obvious. Specifically, the modification suggested by Chi would be to employ a semiconductor device of claim 13, wherein the intermediate epitaxial growth enhancement layer is present in a portion of the semiconductor fin protruding outside the isolation insulating layer, and the gate dielectric layer covers the protruding and intermediate epitaxial growth enhancement layers. The rationale for this obvious modification is that the Chi multi-layer stack provides multi-value logic ([0019, 35]) in a single-fin footprint.
Allowable Subject Matter
Claims 4 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 4, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including the semiconductor device of claim 3, wherein the upper epitaxial growth enhancement layer includes an oxide of one of Si, SiP and SiGe.
Regarding Claim 11, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including the semiconductor device of claim 9, wherein at least one of the plurality of epitaxial growth enhancement layers is made of an oxide of one of Si, SiGe and SiP.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
Prosecution Insights