DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I—Claims 1 – 16—and Species II—as presented in at least Fig. 3 – 15—in the reply filed on 17 June 2026 is acknowledged.
Claims 4, 8, 12, & 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 June 2026.
Status of the Claims
Pending Claims 1 – 16 & 21 – 24
Withdrawn by Applicant Claims 4, 8, 12, & 15
Withdrawn by Examiner None
Cancelled Claims 17 – 20
New Claims 21 – 24
Examined Claims 1 – 3, 5 – 7, 9 – 11, 13 – 14, 16, & 21 – 24
Drawings
The drawings are objected to as being inconsistent. Specifically, Fig. 1A & 3A – 40A appear to reference a right-handed coordinate system while the corresponding coordinate system of Fig. 1B & 3B – 40B appears to be left-handed. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 3, 5, 7, 10 & 13 – 14 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by XIE (US 20230178553 A1).
Regarding Claim 1,
XIE discloses:
A method (Fig. 26 - 61) comprising:
forming (Fig. 41A; Par. 151 – 154) a frontside source/drain trench (left trench, which does not include 234);
forming (Fig. 42A; Par. 155) a dummy source/drain (left 236) in the frontside source/drain trench (left trench);
forming (Fig. 43A; Par. 156 – 159) an upper source/drain (left 238) in the frontside source/drain trench (left trench),
wherein the upper source/drain (left 238) is disposed over the dummy source/drain (left 236);
exposing (Fig. 54A; Par. 175) a backside of the dummy source/drain (right 236);
Note, the identified elements have switched from left to right, as the device has been rotated π radians in the plane of the page, starting at Fig. 54.
Note, “completely exposing a backside of the dummy source/drain” clearly has a different scope than “exposing a backside of the dummy source/drain”. Yet, “exposing a backside of the dummy source/drain” may be construed to mean “completely exposing a backside of the dummy source/drain” under a broadest reasonable interpretation. By analogy, “exposing a backside of the dummy source/drain” may be construed to mean “partially exposing a backside of the dummy source/drain” under a broadest reasonable interpretation. That is, a backside of the right 236 is—partially—exposed in Fig. 54A, as 200 and 202 have been removed, but 234 remains.
removing (Fig. 58A; Par. 180) the dummy source/drain (right 236) to form a backside source/drain trench (272); and
Note, “completely removing the dummy source/drain” clearly has a different scope than “removing the dummy source/drain”. Yet, “removing the dummy source/drain” may be construed to mean “completely removing the dummy source/drain” under a broadest reasonable interpretation. By analogy, “removing the dummy source/drain” may be construed to mean “partially removing the dummy source/drain” under a broadest reasonable interpretation.
forming (Fig. 59A; 181) a lower source/drain (right 274) in the backside source/drain trench (272).
Regarding Claim 2,
XIE discloses:
The method of claim 1, further comprising
forming (Fig. 41A; Par. 151 – 154) a source/drain isolation structure (216/217/234) in the frontside source/drain trench (left trench) before forming (Fig. 43A) the upper source/drain (left 238),
Note, each of the elements 216, 217, and 234 isolate the later-formed source/drains 238 and 274 from each other and/or themselves and/or the later formed gates, as seen in Fig. 61A. As such, under a broadest reasonable interpretation the combination of elements 216, 217, and 234—hereinafter denoted 216/217/234—may be construed to be a source/drain isolation structure.
Note, while 216 and 217 are not themselves formed in the frontside source/drain trench, 234 is formed in the frontside source/drain trench, as the frontside source/drain trench formed in Fig. 41A does not include 234. Therefore, 234 of 216/217/234 is formed in the frontside source/drain trench in Fig. 41A before forming the left 238 in Fig. 43A.
wherein the source/drain isolation structure (234 of 216/217/234) is disposed over the dummy source/drain (left 236).
(As seen in Fig. 42A)
Note, “directly over the dummy source/drain” clearly has a different scope than “over the dummy source/drain”. Yet, “over the dummy source/drain” may be construed to mean “directly over the dummy source/drain” under a broadest reasonable interpretation. By analogy, “over the dummy source/drain” may be construed to mean “indirectly over the dummy source/drain” under a broadest reasonable interpretation.
Regarding Claim 3,
XIE discloses:
The method of claim 2,
wherein the forming (Fig. 41A) the source/drain isolation structure (216/217/234) includes
forming a contact etch stop layer (216) and
Note, Fig. 59A; Par. 181 shows the removal of a portion of 234 via etching, which stops upon contact with 216. Therefore, under a broadest reasonable interpretation, 216 may be construed to be a contact etch stop layer.
forming an interlayer dielectric layer (217).
Note, as per Par. 141, 217 is a dielectric layer. And, as seen in the figures of this embodiment, 217 is disposed between other layers. Therefore, under a broadest reasonable interpretation, 217 may be construed to be an interlayer dielectric layer.
Regarding Claim 5,
XIE discloses:
The method of claim 1, further comprising
replacing (Fig. 54A – 57A) a semiconductor mesa (200) with a backside insulation layer (270) after exposing (Fig. 54A) the backside of the dummy source/drain (right 236) and before removing (Fig. 58A) the dummy source/drain (right 236).
Note, Fig. 54A – 57A show 270 temporarily taking the place of 200 as the outermost layer opposite 266. Therefore, under a broadest reasonable interpretation, Fig. 54A – 57A show replacing 200 with 270.
Note, a “mesa” may be broadly interpreted as any finite structure with a substantially planar upper surface bounded by lateral side surfaces. Accordingly, under a broadest reasonable interpretation, the claimed “semiconductor mesa” may be construed to be the disclosed “semiconductor substrate 200”, as seen in at least Fig. 53A.
Regarding Claim 7,
XIE discloses:
The method of claim 1,
wherein the forming (Fig. 42A) the dummy source/drain (left 236) in the frontside source/drain trench (left trench) includes depositing (Par. 155) a dummy source/drain material in the frontside source/drain trench (left trench) and etching back (Par. 155) the dummy source/drain material.
Note, XIE identifies 236 as a “dielectric material structure” in Par. 155 and throughout the disclosure. XIE also identifies 234 as an “inner spacer dielectric material” in Par. 155 and throughout the disclosure. However, in Par. 155, XIE also misidentifies 234 as the “dielectric material structure”, which is a self-evident clerical error based on the context of both Par. 155, specifically, and the disclosure, in general.
Regarding Claim 10,
XIE discloses:
A method (Fig. 26 – 61) comprising:
forming (Fig. 41A; Par. 151 – 154) a first source/drain trench (left trench, which does not include 234) in a source/drain region (region later occupied by source/drains 238 and 274, as seen in Fig. 61A) adjacent to an upper semiconductor layer (Fig. 41A: upper 208s) and a lower semiconductor layer (Fig. 41A: lower 208s), wherein
the upper semiconductor layer (upper 208s) is disposed over the lower semiconductor layer (lower 208s),
the lower semiconductor layer (lower 208s) is disposed over a substrate (Fig. 41A: 200/202), and
the first source/drain trench (left trench) extends into the substrate (202 of 200/202);
forming (Fig. 42A; Par. 155) a dummy source/drain (left 236) in the first source/drain trench (left trench), wherein
the dummy source/drain (left 236) is disposed in the substrate (202 of 200/202),
the dummy source/drain (left 236) is adjacent to the lower semiconductor layer (lower 208s), and
the dummy source/drain (left 236) is below the upper semiconductor layer (upper 208s);
forming (Fig. 43A; Par. 156 – 159) an upper source/drain (left 238) in the first source/drain trench (left trench) over the dummy source/drain (left 236), wherein
the upper source/drain (left 238) is adjacent to the upper semiconductor layer (upper 208s);
after forming (Fig. 43A) the upper source/drain (left 238), removing (Fig. 58A; Par. 180) the dummy source/drain (right 236) to form a second source/drain trench (272) in the source/drain region, wherein
Note, identified left-elements have switched to right-elements, as the device has been rotated π radians in the plane of the page, starting at Fig. 54.
Note, “completely removing the dummy source/drain” clearly has a different scope than “removing the dummy source/drain”. Yet, “removing the dummy source/drain” may be construed to mean “completely removing the dummy source/drain” under a broadest reasonable interpretation. By analogy, “removing the dummy source/drain” may be construed to mean “partially removing the dummy source/drain” under a broadest reasonable interpretation.
the second source/drain trench (272) is disposed adjacent to the lower semiconductor layer (previously lower/now upper 208s); and
Note, identified upper/lower-elements have switched to lower/upper-elements, as the device has been rotated π radians in the plane of the page, starting at Fig. 54.
forming (Fig. 59A; 181) a lower source/drain (right 274) in the second source/drain trench (272), wherein
the lower source/drain (right 274) is adjacent to the lower semiconductor layer (previously lower/now upper 208s).
Regarding Claim 13,
XIE discloses:
The method of claim 10, further comprising:
replacing (Fig. 54A – 57A) the substrate (200/202) with a backside dielectric layer (270) before removing (Fig. 58A) the dummy source/drain (right 236) to form the second source/drain trench (272); and
Note, Fig. 54A – 57A show 270 temporarily taking the place of 200/202 as the outermost layer opposite 266. Therefore, under a broadest reasonable interpretation, Fig. 54A – 57A show replacing 200/202 with 270.
selectively (Par. 180) removing (Fig. 58A) the dummy source/drain (right 236) relative to the backside dielectric layer (270).
Regarding Claim 14,
XIE discloses:
The method of claim 10,
wherein the removing (Fig. 58A) the dummy source/drain (right 236) to form the second source/drain trench (272) in the source/drain region includes (region later occupied by source/drains 238 and 274, as seen in Fig. 61A) completely removing the dummy source/drain (right 236) from the source/drain region (region later occupied by source/drains 238 and 274, as seen in Fig. 61A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 & 9 are rejected under 35 U.S.C. 103 as being unpatentable over XIE.
Regarding Claim 6,
XIE discloses:
The method of claim 1,
wherein the removing (Fig. 58A) the dummy source/drain (right 236) to form the backside source/drain trench (272) includes performing an etching process (Par. 180).
XIE does not disclose:
performing the etching process (Par. 180) without an etch mask.
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of XIE such that an etch mask is explicitly not required to satisfy performing the etching process without an etch mask, as XIE expressly teaches that the dummy source/drain is selectively etched (XIE Par. 180) and makes no mention or illustration of an associated etch mask. Further, such selectivity permits the dummy source/drain to be removed without requiring an etch mask. Therefore, the express teaching of selective etching and lack of mention of an associated etch mask in XIE would have led one having ordinary skill in the art to perform the claimed etching process without an etch mask with a reasonable expectation of success. Accordingly, the claimed invention would have been obvious in view of the teachings in XIE, consistent with KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). See also MPEP 2143(I)(G).
Regarding Claim 9,
XIE discloses:
The method of claim 1, wherein
the frontside source/drain trench (Fig. 41A: left trench) has a first aspect ratio,
the backside source/drain trench (Fig. 58A: 272) has a second aspect ratio.
XIE does not disclose:
the first aspect ratio is greater than the second aspect ratio.
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of XIE such that the relative dimensions of the first aspect ratio and the second aspect ratio satisfy the first aspect ratio is greater than the second aspect ratio in XIE, as the only claimed difference between the invention of XIE and the claimed invention is the recitation of the relative dimensions of the first aspect ratio and the second aspect ratio. Further, an invention having said claimed relative dimensions would not alter the function of the device components formed in said trenches. Therefore, an invention having said relative dimensions would not perform differently than the invention of XIE. Accordingly, the claimed invention is not patentably distinct from that of the prior art, consistent with Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). See MPEP 2144.04(IV)(A).
Allowable Subject Matter
Claims 21 – 24 are allowed.
The following is the Examiner’s statement of reasons for allowance:
Allowability under 35 U.S.C. 102 and/or 35 U.S.C. 103:
The closest prior art to the present invention is XIE (US 20230178553 A1).
XIE discloses:
A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.
Regarding Independent Claim 21 and its dependent claims, Claims 22 – 24,
There is no teaching or prior art to provide:
A method comprising:
forming a first source/drain trench having a first aspect ratio;
filling a first portion of the first source/drain trench with a sacrificial source/drain, wherein
the sacrificial source/drain is formed of a first semiconductor material…
filling a second portion of the first source/drain trench with a first source/drain…
after filling the second portion of the first source/drain trench with the first source/drain, removing the sacrificial source/drain to form a second source/drain trench…
Missing elements in the closest art gives rise to the innovation in the current invention.
Any comments considered necessary by Applicant must be submitted no later than the payment
of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such
submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 11 is objected to as being dependent upon a rejected base claim, Claim 10, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s statement of reasons for indicating allowable subject matter:
The closest prior art to the present invention is XIE (US 20230178553 A1), as above.
Regarding Claim 11,
There is no teaching or prior art to provide:
The method of claim 10,
wherein the forming the dummy source/drain in the first source/drain trench includes epitaxially growing a semiconductor material.
Missing elements in the closest art gives rise to the innovation in the current invention.
Claim 16 is objected to as being dependent upon a rejected base claim, Claim 10, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s statement of reasons for indicating allowable subject matter:
The closest prior art to the present invention is XIE (US 20230178553 A1), as above.
Regarding Claim 16,
There is no teaching or prior art to provide:
The method of claim 10, further comprising
forming a dielectric layer over the dummy source/drain in the first source/drain trench before forming the upper source/drain, wherein
the upper source/drain is formed over the dielectric layer.
Missing required orderings in the closest art gives rise to the innovation in the current invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights