DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Embodiment 1 in the reply filed on 8/25/2026 is acknowledged.
It is noted that some dependent claims are drawn to Embodiment 2 (i.e. wherein the first and second electrical connections are formed by a conductive clip), and are thus withdrawn according to the election.
Claims 3-5, 8, and 11 are drawn to the non-elected Embodiment 2 and are treated as withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 10, 18, 19, 21-23, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over McPherson et al (U.S. Pub #2019/0237439), in view of Okuda et al (U.S. Pub #2013/0335938).
With respect to claim 1, McPherson teaches a semiconductor device assembly comprising:
a substrate (Fig. 1B, 16) having a patterned metal layer (Fig. 1B, 18 and Paragraph 25) disposed thereon;
a first semiconductor die (Fig. 1B, 20 and Paragraph 24) disposed on a first portion (Fig. 1B, 18A) of the patterned metal layer;
a second semiconductor die disposed on the first portion of the patterned metal layer;
a first electrical connection (Fig. 1B, unlabeled bond wire, Paragraph 29) electrically coupling a second portion (Fig. 1B, 18D or 18E) of the patterned metal layer with the first semiconductor die; and
a second electrical connection electrically coupling the second portion of the patterned metal layer with the second semiconductor die,
McPherson does not teach that the second electrical connection is substantially electrically balanced with the first electrical connection.
Okuda teaches a power semiconductor device comprising electrical connections form as bond wires, wherein the electrical connections are balanced when the lengths of the bond wires are equal (Paragraph 20 and 63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the second electrical connection of McPherson to be balanced with the first electrical connection as taught by Okuda in order to achieve the predictable result of providing a high switching speed (Paragraph 20 and 63).
With respect to claim 2, McPherson and Okuda teach that the first electrical connection includes a first bond wire having a first length; and
the second electrical connection includes a second bond wire having a second length, the second length being substantially equal to the first length (Fig. 1B, unlabeled bond wires of McPherson; Paragraph 20 of Okuda).
With respect to claim 6, McPherson teaches that the first semiconductor die includes a first transistor (Fig. 2, SW1); the second semiconductor die (Fig. 2, SW2) includes a second transistor; and the first transistor and the second transistor are connected in parallel (Paragraph 24).
With respect to claim 10, McPherson teaches
a third semiconductor die including a third transistor, the third semiconductor die being disposed on the first portion (Fig. 1B, 18A) of the patterned metal layer;
a fourth semiconductor die including a fourth transistor (Fig. 1B, there are four semiconductor dies 20 on first portion 18A), the fourth semiconductor die being disposed on the first portion of the patterned metal layer;
a third electrical connection (Fig. 1B, unlabeled bond wires) electrically coupling the second portion of the patterned metal layer with a gate terminal of the third transistor; and
a fourth electrical connection electrically coupling the second portion of the patterned metal layer with a gate terminal of the fourth transistor (Paragraph 23),
McPherson does not teach
the third electrical connection and the fourth electrical connection being, respectively, substantially electrically balanced with the first electrical connection and the second electrical connection.
Okuda teaches a power semiconductor device comprising electrical connections form as bond wires, wherein the electrical connections are balanced when the lengths of the bond wires are equal (Paragraph 20 and 63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the third and fourth electrical connections of McPherson to be balanced with the first electrical connection as taught by Okuda in order to achieve the predictable result of providing a high switching speed.
With respect to claim 18, McPherson teaches a semiconductor device assembly comprising:
a substrate (Fig. 1B, 16) having a patterned metal layer (Fig. 1B, 18 and Paragraph 25) disposed thereon;
a first semiconductor die (Fig. 1B, 20 and Paragraph 24) including a first transistor, the first semiconductor die being disposed on a first portion of the patterned metal layer (Fig. 1B, 18A);
a second semiconductor die including a second transistor, the second semiconductor die being disposed on the first portion of the patterned metal layer;
a first bond wire (Fig. 1B, unlabeled bond wires, Paragraph 29) implementing a first electrical connection between a second portion of the patterned metal layer (Fig. 1B, 18D) and a gate terminal of the first transistor (Paragraph 23); and
a second bond wire implementing a second electrical connection between the second portion of the patterned metal layer (Fig. 1B, 18D) and a gate terminal of the second transistor.
McPherson does not teach that the second electrical connection is substantially electrically balanced with the first electrical connection.
Okuda teaches a power semiconductor device comprising electrical connections form as bond wires, wherein the electrical connections are balanced when the lengths of the bond wires are equal (Paragraph 20 and 63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the second electrical connection of McPherson to be balanced with the first electrical connection as taught by Okuda in order to achieve the predictable result of providing a high switching speed.
With respect to claim 19, McPherson and Okuda teach that the first bond wire has a first length; and the second bond wire has a second length, the second length being substantially equal to the first length (Fig. 1B, unlabeled bond wires of McPherson; Paragraph 20 of Okuda).
With respect to claim 21, McPherson teaches a semiconductor device assembly comprising:
a substrate (Fig. 1B, 16) having a patterned metal layer (Fig. 1B, 18 and Paragraph 25) disposed thereon;
a first semiconductor die (Fig. 1B, 20 and Paragraph 24) including a first transistor, the first semiconductor die being disposed on a first portion (Fig. 1B, 18A) of the patterned metal layer;
a second semiconductor die (Fig. 1B, 20 and Paragraph 24) including a second transistor, the second semiconductor die being disposed on the first portion of the patterned metal layer;
a first bond wire (Fig. 1B, unlabeled bond wire, Paragraph 29) implementing a first electrical connection between a second portion (Fig. 1B, 18D) of the patterned metal layer and a gate terminal of the first transistor (Paragraph 23), the first bond wire having a first length; and
a second bond wire implementing a second electrical connection between the second portion of the patterned metal layer and a gate terminal of the second transistor, the second bond wire having a second length,
McPherson does not teach that the second length being substantially equal to the first length.
Okuda teaches a power semiconductor device comprising electrical connections form as bond wires, wherein the electrical connections are balanced when the lengths of the bond wires are equal (Paragraph 20 and 63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the second electrical connection of McPherson to be balanced with the first electrical connection as taught by Okuda in order to achieve the predictable result of providing a high switching speed (Paragraph 20 and 63).
With respect to claim 22, McPherson teaches that the first bond wire and the second bond wire are substantially parallel (Fig. 1B, unlabeled bond wires).
With respect to claim 23, McPherson does not teach that the first electrical connection is substantially electrically balanced with the second electrical connection.
Okuda teaches a power semiconductor device comprising electrical connections form as bond wires, wherein the electrical connections are balanced when the lengths of the bond wires are equal (Paragraph 20 and 63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the second electrical connection of McPherson to be balanced with the first electrical connection as taught by Okuda in order to achieve the predictable result of providing a high switching speed.
With respect to claim 26, McPherson teaches that a gate signal lead (Fig. 1B, terminal portion of 18D) is physically coupled to the second portion of the patterned metal layer.
Claims 7, 9, 20, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over McPherson2019 and Okuda, in view of McPherson et al (U.S. Pub #2020/0395322).
With respect to claim 7, McPherson2019 does not teach a conductive clip electrically coupling a third portion of the patterned metal layer with: a source terminal of the first transistor; and a source terminal of the second transistor.
McPherson2020 teaches a conductive clip (Fig. 3, 66) electrically coupling a third portion of the patterned metal layer with: a source terminal (Fig. 3, 58 and Paragraph 34) of the first transistor; and a source terminal of the second transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the semiconductor dies and electrical connections of McPherson2019 such that a conductive clip couples a third portion to source terminals of the first and second transistors as taught by McPherson2020 in order to provide a balanced connection to reduce voltage differences across the device to improve device performance (Paragraph 36).
With respect to claim 9, McPherson2020 teaches that an electrical conduction path between the third portion of the patterned metal layer and the source terminal of the first transistor is substantially electrically balanced with an electrical conduction path between the third portion of the patterned metal layer and the source terminal of the second transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the semiconductor dies and electrical connections of McPherson2019 such that a conductive clip couples a third portion to source terminals of the first and second transistors as taught by McPherson2020 in order to provide a balanced connection to reduce voltage differences across the device to improve device performance (Paragraph 36).
With respect to claim 20 and 24, McPherson2019 does not teach
a conductive clip electrically coupling a third portion of the patterned metal layer with:
a source terminal of the first transistor; and
a source terminal of the second transistor,
the conductive clip implementing:
a first electrical conduction path between the third portion of the patterned metal layer and the source terminal of the first transistor; and
a second electrical conduction path between the third portion of the patterned metal layer and the source terminal of the second transistor,
the first electrical conduction path being substantially electrically balanced with the second electrical conduction path.
McPherson2020 teaches
a conductive clip (Fig. 3, 66) electrically coupling a third portion of the patterned metal layer with:
a source terminal (Fig. 3, 58 and Paragraph 34) of the first transistor; and
a source terminal of the second transistor,
the conductive clip implementing:
a first electrical conduction path between a third portion (Fig. 3, 42) of a patterned metal layer and the source terminal of the first transistor; and
a second electrical conduction path between a third portion of a patterned metal layer (Fig. 3, 42) and the source terminal of the second transistor,
the first electrical conduction path being substantially electrically balanced with the second electrical conduction path (Paragraph 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the semiconductor dies and electrical connections of McPherson2019 such that a conductive clip couples a third portion to source terminals of the first and second transistors as taught by McPherson2020 in order to provide a balanced connection to reduce voltage differences across the device to improve device performance (Paragraph 36).
With respect to claim 25, McPherson2020 the first electrical conduction path is substantially electrically balanced with the second electrical conduction path (Paragraph 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the semiconductor dies and electrical connections of McPherson2019 such that the first and second electrical conduction paths are substantially electrically balanced as taught by McPherson2020 in order to provide a balanced connection to reduce voltage differences across the device to improve device performance (Paragraph 36).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
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