DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Drawings 3
IV. Claim Rejections - 35 USC § 103 4
A. Claims 1-6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0367401 (“Kim”) in view of US 2021/0102294 (“Miljkovic”) and US 4,323,914 (“Berndlmaier”). 4
B. Claims 7, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Miljkovic and Berndlmaier, as applied to claim 1 above, and further in view of US 6,577,013 (“Glenn”). 10
C. Claims 11, 12, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Miljkovic and Berndlmaier, as applied to claim 1 above, and further in view of US 2024/0153886 (“Seong”). 12
V. Allowable Subject Matter 15
VI. Pertinent Prior Art 16
Conclusion 17
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of the species formed by subspecies groups A-7, B-2, and C-7, in the reply filed on 08/18/2026, is acknowledged. Applicant indicates that claims 1-12 and 18-20 read on the elected species.
The claims drawn to the non-elected species may be entitled to rejoinder under the conditions explained in the Requirement for Election/Restriction at page 5, third paragraph.
III. Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 274 in Fig. 7B.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0367401 (“Kim”) in view of US 2021/0102294 (“Miljkovic”) and US 4,323,914 (“Berndlmaier”).
Claim 1 reads,
1. (Currently Amended) A semiconductor package, comprising:
[1] a first semiconductor die disposed over a first substrate;
[2] a plurality of second semiconductor dies disposed over the first semiconductor die;
[3] a plurality of first connectors arranged between and electrically connecting the first semiconductor die and the first substrate;
[4] a plurality of second connectors arranged between and electrically connecting two of the second semiconductor dies;
[5] a first dielectric layer encapsulating the plurality of second connectors; and
[6a] a dielectric coating, different from the first dielectric layer,
[6b] conformally formed on exposed surfaces of the plurality of first connectors and
[6c] laterally surrounding the first dielectric layer,
[7] wherein a plurality of air gaps are arranged between the plurality of first connectors.
With regard to claim 1, Kim discloses, generally in Figs. 2, 4B, and 5,
1. (Currently Amended) A semiconductor package, comprising:
[1] a first semiconductor die [100 in Figs. 2, 4B or 700 in Fig. 5] disposed over a first substrate [600 in Figs. 2, 4B or 500 in Fig. 5, respectively] [¶¶ 19, 58, 59, 66];
[2] a plurality of second semiconductor dies 200-1 to 200-4 [¶ 67] disposed over the first semiconductor die 100, 700;
[3] a plurality of first connectors 220, 720 [¶¶ 27, 68] arranged between and electrically connecting the first semiconductor die 100, 700 and the first substrate 600, 500;
[4] a plurality of second connectors 220 [¶ 30] arranged between and electrically connecting two of the second semiconductor dies 200-1 to 200-4 [best shown in Fig. 2];
[5] a first dielectric layer [300b in Figs. 2, 4B, 5 (¶¶ 45-46) or 300-1 to 300-4 in Fig. 3 (¶ 49)] encapsulating the plurality of second connectors 220; and
[6a]-[6c] … [not taught] …
[7] … [not taught] …
With regard to features [6a]-[6c] of claim 1 and claim 4,
[6a] a dielectric coating, different from the first dielectric layer,
[6b] conformally formed on exposed surfaces of the plurality of first connectors and
[6c] laterally surrounding the first dielectric layer,
4. (Original) The semiconductor package of claim 1, wherein the dielectric coating comprises parylene.
Kim does not discuss the dielectric coating and does not, consequently, disclose the limitations of features [6a]-[6c] and [7] of claim 1.
Miljkovic is drawn to the same endeavor as that in the Instant Application of vapor depositing a protective parylene coating on an entire packaged semiconductor device in order to protect it from the coolant liquid during immersion cooling (Miljkovic: Title; Abstract; Figs. 1A-3C; e.g. ¶¶ 54, 58, 61-66). In this regards, Miljkovic states,
[0054] More specifically, this disclosure discusses use of immersion cooling of electronics directly in water. To do so, a printed circuit board (PCB) and disposed electronics can be electrically-insulated from water in nano-layers such as Parylene C coatings. Demonstrated experimentally is the effectiveness of conformal layers of Parylene C as thin as 1 μm in preventing current from leaking between the electronic components and the surrounding water when the system is subjected to voltages up to 200 Volts.
(Miljkovic: ¶ 54; emphasis added)
As with Kim and the Instant Application, the electronics are attached to the printed circuit board (PCB) with solder balls (Miljkovic: ¶ 91).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to mount the packaged semiconductor device of Kim to a PCB and then vapor deposit a conformal parylene coating onto the entire assembly, as taught in Miljkovic, in order to provide a protective coating to the package for immersion cooling, as also taught in Miljkovic. As such, Miljkovic may be seen as an improvement to Kim in this aspect.
Then, with regard to feature [7] of claim 1, it is not clear from Miljkovic whether or not there is an air gap between the first connectors 720 after the parylene deposition.
Berndlmaier, like Miljkovic, teaches that it is very old (as of at least 1982) and well known to vapor deposit parylene onto a semiconductor device 2 mounted by solder balls 12 to a substrate 1 to form a protective parylene coating 5 over all of the exposed surfaces including the substrate, the semiconductor device chip 2, inter alia, including the remaining exposed surfaces of the solder balls 12, as shown in Figs. 1 and 2 of Berndlmaier (Berndlmaier: col. 9, line 58 to col. 10, line 19). Figs. 1 and 2 of Berndlmaier further show that air gaps remain between the coated solder balls 12. The protective parylene coating 5 protects the device form the liquid metal coolant 6:
The thermal liquid [6] is contained within the cavity define by the cover and substrate. The chips (or chip) and the flip chip connections are protected from contamination and the deleterious effects of the thermally conductive liquid [6] by a parylene film [5] enveloping same.
(Berndlmaier: Abstract)
This need is satisfied after seating of the frame 3 by deposition of a conformal coating 5 consisting of a material such as parylene, whose penetration and continuity of coverage are controllable in films thin enough to afford protection without substituting a significant layer of thermal insulation. As shown in the drawing, this conformal coating fully encompasses all sides of chip 2 and the solder connections 12. The coating 5, by extending to cover the inside walls of the frame 3, also creates a two directional supplementary seal along seam 4 or the walls of the frame 3. This permits considerable latitude in the selection of materials and or techniques to be used for fabrication of the frame 3 and seam 4.
(Berndlmaier: col. 10, lines 26-39; emphasis added)
Thus, Berndlmaier, like Miljkovic, teaches that the parylene coating 5 conformally coats all exposed surfaces particularly the exposed surfaces of the solder balls 12, leaving air gaps, as required by feature [7] of claim 1.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to ensure the vapor-deposited parylene coating of Miljkovic and/or Berndlmaier formed over the entire mounted semiconductor device of Kim on the PCB of Kim conformally coats the first connectors, i.e. solder balls 220, 720 of Kim, leaving air gaps between, as taught in Berndlmaier because the coating is conformal and because one having ordinary skill in the art would recognize that leaving air gaps between the coated solder balls 220, 720 would leave space for the cooling fluid of Miljkovic to flow, thereby aiding cooling.
Based on the foregoing, Kim modified according to Miljkovic and Berndlmaier, teaches the limitations of features [6a]-[6c] and [7] of claim 1 and claim 4 are met as follows:
[6a] a dielectric coating [parylene of Miljkovic], different from the first dielectric layer [300b in Figs. 2, 4B, 5 (Kim: ¶¶ 45-46) or 300-1 to 300-4 in Fig. 3 (Kim: ¶ 49)],
[6b] conformally formed on exposed surfaces of the plurality of first connectors [because the entire package and PCB are coated, as taught by Miljkovic, thereby forming parylene on all exposed surfaces, as evidenced by Berndlmaier] and
[6c] laterally surrounding the first dielectric layer 300b or 300-1 to 300-4 [again, because the entire package and PCB are coated, as taught by Miljkovic, thereby forming parylene on all exposed surfaces, as evidenced by Berndlmaier],
[7] wherein a plurality of air gaps are arranged between the plurality of first connectors [220, 720 of Kim] [as taught by Berndlmaier, Figs. 1 and 2].
4. (Original) The semiconductor package of claim 1, wherein the dielectric coating comprises parylene [as taught in each of Miljkovic and Berndlmaier].
This is all of the limitations of claims 1 and 4.
With regard to claim 2, Kim modified according to Miljkovic and Berndlmaier further teaches,
2. (Original) The semiconductor package of claim 1, wherein the air gaps are configured to allow passage of liquid coolant under an immersion cooling operation.
“[A]pparatus claims cover what a device is, not what a device does.” See Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). See MPEP 2114(II). The immersion cooling is an intended use of the claimed package. As such, all that is required is that the device taught by Kim modified according to Miljkovic and Berndlmaier is capable of “allow passage of liquid coolant under an immersion cooling operation”.
It is held, absent evidence to the contrary, that the air gaps of Berndlmaier that result in Kim are capable of allowing passage of liquid coolant under the immersion cooling of Miljkovic. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to claim 3, Kim modified according to Miljkovic and Berndlmaier further teaches,
3. (Original) The semiconductor package of claim 1, wherein the dielectric coating [of Miljkovic or Berndlmaier] is further formed on an exposed lower surface of the first semiconductor die [100 or 700 of Kim] and an exposed upper surface of the first substrate [600 or 500 of Kim] to define the air gaps [because all exposed surfaces are coated, as taught by Berndlmaier (supra)].
With regard to claims 5 and 6, Kim further discloses,
5. (Original) The semiconductor package of claim 1, wherein the first dielectric layer [300b in Fig. 5 (¶¶ 45-46) or 300-1 to 300-4 in Fig. 3 (¶ 49)] fills spaces between two of the second semiconductor dies 200-1 to 200-4.
6. (Original) The semiconductor package of claim 1, wherein each of the first semiconductor die 700, the plurality of second semiconductor dies 200-1 through 200-4, and the first substrate 600 comprises a plurality of first through vias 730, 230, 630 [respectively, as shown in Fig. 4B].
Claim 18 reads,
18. (Currently Amended) A method of forming a semiconductor package, comprising:
[1] forming a plurality of first connectors over a first semiconductor die;
[2] bonding the first semiconductor die to a substrate through the plurality of first connectors;
[3a] forming a die stack over the first semiconductor die, wherein
[3b] the die stack comprises a plurality of second semiconductor dies,
[3c] a plurality of second connectors between two of the second semiconductor dies, and
[3d] a first dielectric layer encapsulating the plurality of second connectors; and
[4a] depositing a dielectric coating, different from the first dielectric layer, on exposed surfaces of
[4b] the substrate,
[4c] the plurality of first connectors,
[4d] the first semiconductor die,
[4e] the plurality of second semiconductor dies, and
[4f] the first dielectric layer,
[5] wherein the deposition of the dielectric coating leaves a plurality of air gaps between the plurality of first connectors.
Each of the limitations of claim 18 have been addressed under claim 1 and 3-5.
B. Claims 7, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Miljkovic and Berndlmaier, as applied to claim 1 above, and further in view of US 6,577,013 (“Glenn”).
Claim 7 reads,
7. (Original) The semiconductor package of claim 1, further comprising a first heat spreader arranged between the first semiconductor die and the plurality of second semiconductor dies.
The prior art of Kim modified in view of Miljkovic and Berndlmaier, as explained above, teaches each of the features of claim 1.
Kim does not disclose the claimed heat spreader.
Glenn, like Kim, teaches a semiconductor device package including a stack of semiconductor dies (Glenn: Title; Abstract; e.g. Figs. 5-6, 10-11). Glenn further teaches including heat spreaders 62 between adjacent chips 16 in the chip stack (Glenn: Figs. 10-11; col. 8, line 46 to col. 9, line 22).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include heat spreaders between each of the first die 100 or 700 and the second dies 200-1 to 200-4 in Kim, in order to aid removal of heat from the chip stack, as taught in Glenn.
This is all of the limitations of claim 7.
Claim 9 reads,
9. (Original) The semiconductor package of claim 1, further comprising
[1] a second heat spreader coupled to the first substrate,
[2] wherein the second heat spreader comprises a through via extending through the second heat spreader.
The inclusion of a heat spreader 62 of Glenn between the first die 100 or 700 of Kim and the first substrate 600 or 500, respectively, of Kim is obvious for the same reason as explained under claim 7, i.e. to aid in removing heat from the first die 100, 700, i.e. the logic die which would be expected to produce more heat than each of the memory dies 200-1 to 200-4.
In addition, Glenn teaches conductive through vias 42 extending through each of the heat spreaders 62 in order maintain the electrical connection between the dies 16 in the stack to an underlying interposer or PCB (not shown) (Glenn: col. 5, line 55 to col. 6, line 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include through vias through the second heat spreader in order to maintain electrical connection between the first die 100 or 700 and the first substrate 600 or 500, respectively, of Kim.
This is all of the limitations of claim 9.
Claim 10 reads,
10. (Original) The semiconductor package of claim 1, further comprising
[1] a third heat spreader disposed over the plurality of second semiconductor dies, and the first substrate
[2] wherein the dielectric coating is further formed on exposed surfaces of the third heat spreader and the first substrate.
With regard to feature [1] of claim 10, the inclusion of a heat spreader 62 of Glenn over the plurality of second semiconductor dies 200-1 to 200-4 of Kim is obvious for the same reason as explained under claim 7, i.e. to aid in removing heat from the uppermost die 200-4, as well as the entire die stack 200-1 to 200-4.
With regard to feature [2] of claim 10, as above, because all exposed surfaces are coated, as taught by Berndlmaier, the exposed surfaces of the third heat spreader and the first substrate of Kim would be coated with parylene of Miljkovic or Berndlmaier during vapor deposition.
This is all of the limitations of claim 10.
C. Claims 11, 12, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Miljkovic and Berndlmaier, as applied to claim 1 above, and further in view of US 2024/0153886 (“Seong”).
Claim 19 and 20 read,
19. (Original) The method of claim 18, further comprising
[1] forming a plurality of enhancing structures between the first semiconductor die and the substrate,
[2] wherein the plurality of enhancing structures are formed on a periphery of the first semiconductor die, and
[3] wherein the dielectric coating is further formed on exposed surfaces of the plurality of enhancing structures.
20. (Original) The method of claim 19, wherein the plurality of enhancing structures at least cover sidewalls of the first semiconductor die, or extend to a depth of the substrate.
The prior art of Kim in view of Miljkovic and Berndlmaier, as explained above, teaches each of the features of claim 18.
Kim does not disclose the claimed “enhancing structures”.
Seong, like Kim, is drawn to a semiconductor package including a stack of semiconductor dies 210/220/230 (Seong: ¶¶ 115-116; Figs. 14-17, 22). Seong further teaches an enhancement structures, i.e. buffering structures, e.g. 310/216 (Seong: Figs. 12-13; ¶¶ 73-77) and 322 (Seong: Figs. 16-17; ¶¶ 82, 85), in order to protect the side surfaces of the die 210:
[0086] According to some embodiments, the side surface of the lower semiconductor chip 210 may be protected by the second buffering structure 320. Accordingly, it may be possible to improve the structural stability of the semiconductor package.
(Seong: ¶ 86; emphasis added)
The buffer structures are provided the corners of the first die 210, between the first die and the substrate 100, as shown in Figs. 3-8, or all of the way around the side surfaces as shown in Fig. 9.
Thus, Seong teaches the following features of claims 19 and 20:
19. (Original) The method of claim 18, further comprising
[1] forming a plurality of enhancing structures 310/216, 322 between the first semiconductor die 210 and the substrate 100,
[2] wherein the plurality of enhancing structures 310/216, 322 are formed on a periphery of the first semiconductor die 210 [as shown in Figs. 3-9 of Seong], and
[3] …
20. (Original) The method of claim 19, wherein the plurality of enhancing structures 322 at least cover sidewalls of the first semiconductor die 210 [as shown in Figs. 16-17 of Seong].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the enhancing structures of Seong between the first substrate 600 or 500 of Kim surrounding the corners, and optionally the sidewalls of the first semiconductor die 100 or 700, respectively, of Kim in order to protect the corners of the first semiconductor die 100 or 700 and thereby “improve the structural stability of the semiconductor package”, as taught by Seong. As such, Seong may be seen as an improvement to Kim in this aspect. (See MPEP 2143.)
Finally, with regard to feature [3] of claim 19, as explained above, because all exposed surfaces are coated, as taught by Berndlmaier, the exposed surfaces of the enhancing structure of Soeng, used in Kim would be coated with parylene of Miljkovic or Berndlmaier during vapor deposition.
This is all of the limitations of claims 19 and 20.
Claims 11 and 12 read,
11. (Currently Amended) A semiconductor package, comprising:
[1] a first semiconductor die arranged over a substrate;
[2] a plurality of second semiconductor dies over the first semiconductor die;
[3] a plurality of first connectors arranged between and electrically connecting the first semiconductor die and the substrate;
[4] a plurality of second connectors arranged between and electrically connecting two of the second semiconductor dies;
[5] a first dielectric layer encapsulating the plurality of second connectors;
[6a] a plurality of enhancing structures adjacent to the first semiconductor die,
[6b] wherein the plurality of enhancing structures are arranged proximal to the plurality of first connectors and the substrate, surrounding, or over the first semiconductor die; and
[7a] a dielectric coating,
[7b] different from the first dielectric layer,
[7c] conformally formed on exposed surfaces of the plurality of first connectors and the plurality of enhancing structures, and
[7d] laterally surrounding the first dielectric layer.
12. (Original) The semiconductor package of claim 11, wherein the plurality of enhancing structures are arranged to cover corners of the first semiconductor die from a top-view perspective.
Each of the limitations of features [1]-[5], [7a], [7b], [7d] and most of [7c] of claim 11 has been addressed under the rejection of claim 1. Each of the limitations of features [6a]-[6b], the remainder of feature [7c] of claim 11 and claim 12 has been addressed above under claims 19 and 20.
This is all of the limitations of claims 11-12.
V. Allowable Subject Matter
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 reads,
8. (Original) The semiconductor package of claim 1, further comprising:
[1] a second substrate disposed below the first substrate;
[2] a plurality of third connectors arranged between and electrically connecting the first substrate and the second substrate; and
[3] a second dielectric layer encapsulating the plurality of third connectors,
[4] wherein the dielectric coating is further formed over exposed surfaces of the second substrate and the second dielectric layer.
With regard to claim 8, the embodiment shown in Fig. 4B of Kim further discloses,
8. (Original) The semiconductor package of claim 1, further comprising:
[1] a second substrate 500 disposed below the first substrate 600;
[2] a plurality of third connectors 620 arranged between and electrically connecting the first substrate 600 and the second substrate 500; and
[3]-[4] … [not taught] …
Kim does not disclose the limitations in features [3] and [4].
The prior art does not reasonably teach or suggest—in the context of claim 8—the use of the second dielectric layer encapsulating the third connectors. It is not considered obvious to use the first dielectric encapsulating the second connectors and the second dielectric encapsulating the third connectors while leaving the first connectors exposed from encapsulation by any dielectric, such that the first connectors can be coated with the conformal parylene layer.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2005/0057856 (“Kira”): Figs. 6A-6B and associated text, the protective coating 110 is parylene.
US 6,717,812 (“Pinjala”): Figs. 1, 2, and 5 and associated text.
US 2017/0179001 (“Brunschwiler”): Fig. 1 and associated text.
US 2019/0385931 (“Eid”): at least Figs. 14-24 and associated text.
US 2021/0166991 (“Liu”); Figs. 2, 5, and 6 and associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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