DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: semiconductor structures 500. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “151” in figure 2. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-10 and 13-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation “the stacked layers.” However, the parent claim from which claim 8 depends (claim 1) recites “alternating layers of silicon nitride and silicon oxide” and does not introduce or define “stacked layers.” Because “stacked layers” is not previously introduced with an indefinite article, the use of the definite article “the” in claim 8 lacks proper antecedent basis. As a result, it is unclear whether “the stacked layers” refers to the alternating layers recited in claim 1 or instead refers to a different, undefined set of layers. Accordingly, the scope of claim 8 cannot be determined with reasonable certainty. Claims 9-10 are further rejected by virtue of their dependence upon indefinite claim 8 and because they fail to sure the deficiencies outlined above.
Claim 13 recites “the stacked layers” in limitation iii) and again in limitation vi). However, claim 13 does not previously introduce or define “stacked layers.” Because “stacked layers” is not defined elsewhere in claim 13, the claim fails to clearly identify the structure to which the limitations apply. Accordingly, the scope of claim 13 cannot be determined with reasonable certainty. Claims 14-18 are further rejected by virtue of their dependence upon indefinite claim 8 and because they fail to sure the deficiencies outlined above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 8-9, and 11-20 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Korolik et al. (US 2022/0293430 A1) in view of Yokoyama et al. (US 2022/0199412 A1).
Regarding claim 1, Korolik teaches a semiconductor processing method comprising:
flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate is positioned within the processing region and comprises alternating layers of silicon nitride and silicon oxide (abstract, claim 1, paragraph [0006]);
forming plasma effluents of the fluorine-containing precursor (claim 1, paragraph [0006]);
contacting the substrate with the plasma effluents of the fluorine-containing precursor, wherein the contacting selectively etches an exposed portion of silicon nitride relative to silicon oxide (Abstract, claim 1, paragraphs [0006, 0023]);
Korolik teaches the use of a fluorine-containing precursor in a plasma process to selectively etch silicon nitride in a substrate comprising alternating silicon nitride and silicon oxide layers. Korolik does not teach introducing a phosphorous-and-fluorine-containing precursor into the processing region while maintaining a flow of the fluorine-containing precursor; forming plasma effluents of the phosphorous-and-fluorine-containing precursor; and contacting the substrate with the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor, wherein the contacting selectively etches an exposed portion of silicon oxide.
Yokoyama teaches supplying a process gas that includes both a fluorine gas component and a phosphorus gas component, including phosphorus trifluoride (PF3), during plasma etching (paragraphs [0087], [0092]). Yokoyama further teaches that the combined use of fluorine-containing and phosphorus-containing precursors in a plasma process selectively enhances etching of silicon oxide relative to silicon nitride by forming protective P-O containing film on side wall, thereby improving selectivity and profile control (paragraphs [0137]–[0140]). Yokoyama additionally teaches etching of alternately stacked silicon oxide and silicon nitride layers using such process gases (paragraph [0141])
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the semiconductor process method of Korolik, which teaches selectively etching silicon nitride using a fluorine-containing precursor in a plasma process, to further include introducing a phosphorus-and-fluorine-containing precursor such as PF3 while maintaining the fluorine-containing precursor, as taught by Yokoyama, in order to selectively etch silicon oxide and silicon nitride stack structure. Such a modification represents a predictable use of known plasma etching chemistries to alternately etch different materials within a multilayer structure. Furthermore, the claimed limitations are obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results. See MPEP § 2143(A).
Regarding claim 2, Korolik further teaches wherein the fluorine-containing precursor comprises hydrogen fluoride (HF) (paragraph [0049]).
Regarding claim 3, Korolik as modified by Yokoyama teaches that the phosphorus gas component supplied during plasma etching may include phosphorus trifluoride (PF3) (Yokoyama, paragraph [0088]).
Regarding claim 4, Korolik further teaches wherein a flow rate of the fluorine-containing precursor is greater than or about 100 sccm (that precursor flow rates, including halogen-containing precursors, additive precursors, and total precursor flow, may be controlled in units of standard cubic centimeters per minute (sccm), including values below or about 100 sccm, to control dissociation and etching behavior (paragraph[0060]). It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP § 2144.05 (I).
Regarding claim 5, Korolik teaches controlling additive precursor, halogen-containing precursor, and total precursor flow rates in units of sccm, including flow rates below or about 50 sccm, to control plasma dissociation and etching selectivity (paragraph [0060]).
Korolik doesn’t teach supplying a phosphorous-and-fluorine-containing precursor at a low proportional flow rate relative to a total processing gas flow because Korolik does not disclose phosphorus containing precursors.
Yokoyama teaches supplying a phosphorus-and-fluorine containing precursor, including phosphorus trifluoride (PF3), at controlled flow rates during plasma etching and experimentally evaluates the effect of PF3 flow rate on silicon oxide etching behavior (paragraphs [0136], figs. 8-10). Accordingly, selecting a PF3 flow rate less than or about 50 sccm would have been an obvious matter of routine optimization in view of Yokoyama’s teachings. See MPEP § 2144.05.
Regarding claim 6, Korolik teaches the use of hydrogen fluoride (HF) as the fluorine-containing precursor(paragraph [0049]). Hydrogen fluoride does not contain carbon and is therefore carbon-free.
Regarding claim 8, which recites applying a bias power during plasma processing, Korolik teaches applying a bias power during plasma etching to control ion energy and ion-surface interactions (paragraphs [0045], [0046]), wherein the bias power is applied between the substrate and an electrode in the processing chamber.
Regarding claim 9, Korolik further teaches wherein the bias power is greater than or about 100 W (below or about 100W, paragraph [0046]).
Regarding claim 11, Korolik teaches performing plasma etching at a chamber operating pressure between about 10 mTorr and about 5 Torr, claim 7 (claim 7). It would have been obvious to operate the process at a chamber pressure less than or about 500 mTorr, because selecting a pressure value within a disclosed range constitutes routine optimization of a result-effective variable. See MPEP § 2144.05.
Regarding claim 12, Korolik teaches performing plasma etching at reduced substate temperatures, including temperatures less than or about 0° C (paragraphs [0046],[0059]). Selection of a substrate operating temperature less than or about 0° C within the disclosed temperature condition would have been a matter of routine optimization. See MPEP § 2144.05
Regarding claim 13, Korolik teaches a semiconductor processing method comprising:
i) flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate positioned within the processing region comprises alternating layers of silicon nitride and silicon oxide and further comprises a patterned resist material overlying the alternating layers (claim 13);
ii) forming plasma effluents of the fluorine-containing precursor (claim 13);
iii) contacting the stacked layers with the plasma effluents of the fluorine-containing precursor, wherein the contacting selectively etches an exposed layer of silicon nitride (claim 13);
vii) repeating the above operations for at least a second cycle. (claims 13, 16).
Korolik does not teach flowing a phosphorous-and-fluorine-containing precursor into the processing region with the fluorine-containing precursor; v) forming plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor; or vi) contacting the stacked layers with the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor, wherein the contacting selectively etches an exposed layer of silicon oxide.
Yokoyama teaches supplying a process gas including both a fluorine-containing precursor and a phosphorus trifluoride (PF3), forming plasma effluents thereof , and selectively etching silicon oxide in a stacked silicon oxide and silicon nitride structure (paragraphs [0089], [0092], [0137]-[0141]). Yokoyama further teaches applying such plasma chemistry to stacked of alternately layered silicon oxide and silicon nitride films (paragraph [0141]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the cyclic semiconductor processing method of Korolik by incorporating the oxide-selective plasma chemistry taught by Yokoyama in order to alternately etch silicon nitride and silicon oxide layers within a stacked structure. Such modification represents the predictable use of known plasma etching techniques for processing multilayer silicon-containing films and would have yielded predictable etching results.
Regarding claim 14, Korolik teaches that fluorine-containing precursor further comprises hydrogen. Korolik discloses the use of hydrogen fluoride (HF) as a fluorine-containing precursor during plasma etching (paragraph [0049]). Because HF contains hydrogen, Korolik therefore teaches a fluorine-containing precursor that further comprises hydrogen.
Regarding claims 15-16, Korolik teaches that etching behavior of silicon nitride is controlled through adjustment of known plasma power and precursor flow conditions, and that reducing total flow and/or adjusting pressure may increase etch rate (paragraphs [0046], [0059] - [0060]). It would have been obvious to one of ordinary skill in the art to maintain the fluorine-containing precursor taught by Korolik while additionally introducing a phosphorus-and-fluorine containing precursor, such as PF3, as taught by Yokoyama, and to adjust known plasmas process parameters to achieve an etch rate of the exposed layer greater than or about 250 nm/min or greater than or about 400 nm/min as matter or routine optimization. See MPEP § 2144.05].
Regarding claim 17, Korolik teaches repeating plasma etching operations for at least ten cycles (claim 16). Accordingly, repeating operations i) through vi) for at least ten cycles would have been obvious.
Regarding claim 18, Korolik teaches performing plasma etching at reduced substrate operating temperatures, including temperatures less than or about 0°C (paragraphs [0046], [0059]). Selecting a substrate operating temperature less than or about −20 °C would have been a matter of routine optimization. See MPEP § 2144.05.
Regarding claim 19, Korolik teaches a semiconductor processing method comprising:
flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate positioned within the processing region comprises alternating layers of silicon nitride and silicon oxide (paragraph [0007]);
forming plasma effluents of the fluorine-containing precursor (paragraph [0007]);
contacting the substrate with the plasma effluents of the fluorine-containing precursor, wherein the contacting etches an exposed portion of silicon nitride relative to silicon oxide at a selectivity greater than or about 5:1; (paragraph [0007]).
Korolik does not teach introducing a phosphorous-and-fluorine-containing precursor into the processing region while maintaining a flow of the fluorine-containing precursor; forming plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor; and contacting the substrate with the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor, wherein the contacting etches an exposed portion of silicon oxide relative to silicon nitride
Yokoyama teaches supplying a fluorine-containing precursor together with a phosphorus-and-fluorine-containing precursor, including PF3, forming plasma effluents thereof, and selectively enhancing etching of silicon oxide relative to silicon nitride by formation of a protective P-O containing film (paragraphs [0137]-[0140]). Yokoyama further demonstrates etching selectivity values greater than 5 when using PF3 in combination with fluorine-containing precursor, as shown in Fig. 11 and the corresponding description in paragraph [0148].
It would have been obvious to one of ordinary skill to modify the semiconductor processing method of Korolik by introducing the phosphorus-and-fluorine-containing precursor taught by Yokoyama in order to selectively etch silicon oxide in addition to silicon nitride. Korolik teaches etching silicon nitride relative to silicon oxide with an etching selectivity greater than or about 5:1 using a fluorine-containing plasma chemistry. Yokoyama teaches selectivity etching silicon oxide relative to silicon nitride with an etching selectivity greater than 5 using a phosphorus-and-fluorine containing precursor, including PH3 (See figure 11). Because Korolik and Yokoyama independently teach etching selectivity greater than 5 for their respective plasma chemistries, one of ordinary skill in the art would reasonably expect an etching selectivity greater than or about 5:1 when combining the fluorine-containing precursor of Korolik with the phosphorus-and-fluorine containing precursor of Yokoyama. See MPEP § 2144.05.
Regarding claim 20, Korolik teaches flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber and forming plasma effluents thereof to etch silicon-containing materials (paragraph [0007]).
Korolik does not teach a flow rate ratio of a fluorine-containing precursor to a phosphorous-and-fluorine-containing precursor, because Korolik does not disclose introducing a phosphorous-and-fluorine-containing precursor.
Yokoyama teaches supplying PF3 at low flow rates relative to fluorine-containing gases during plasma etching of silicon-containing films and provides example process gas compositions in which PF3 constitutes a minor from of the total gas flow (paragraphs [0128]-[0139]).
It would have been obvious to one of ordinary skill in the art to select a flow-rate ratio of fluorine-containing precursor to the phosphorus-and fluorine-containing precursor greater than or about 30:1 as a matter of routine optimization, because gas flow-rate ratios are known result-effective variables in plasma etching processes. See MPEP § 2144.05.
Claims 7 and 10 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Korolik in view of Yokoyama, as applied to claim 1 above, and further in view of Orui et al. (US 2022/0148884 A1).
Regarding claim 7, Korolik teaches a plasma processing system including a power supply configured to deliver an adjustable amount of power for generating plasma and controlling plasma characteristics during processing (paragraph[0035]).
Korolik does not teach pulsing the source plasma power during plasma generation.
Orui teaches a plasma etching method for silicon-containing semiconductor substrates in which electrical power is applied in an intermittent or periodic (pulsed) manner to control ion behavior during plasma processing (paragraph [0074]).
It would have been obvious to one of ordinary skill in the art to pulse the source plasma power in the method of Korolik as predictable variation of controlling plasma characteristics during etching of silicon-containing films, yielding predictable results such as controlled plasma density and etch behavior. Furthermore, the claimed limitations are obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results. See MPEP § 2143(A).
Regarding claim 10, Korolik teaches applying a bias power during plasma processing (paragraphs [0045], [0046]).
Korolik does not teach pulsing the bias power wiling contacting the substrate.
Orui teaches intermittently or periodically applying a pulse bias power during plasma processing to control ion behavior at the substrate surface (paragraph [0074]).
Furthermore, the claimed limitations are obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results. See MPEP § 2143(A).
Conclusion
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/JONATHAN L CARTER/Examiner, Art Unit 1713
/JOSHUA L ALLEN/Supervisory Patent Examiner, Art Unit 1713