DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II: Claims 17-20 in the reply filed on 07/23/2026 is acknowledged. Claims 1-16 of non-elected Group I were canceled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-19, 21-26, 28-34 and 36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0009347 A1 to Lin et al. (hereinafter “Lin”).
Regarding claim 17, Lin discloses a method for manufacturing a semiconductor structure, comprising:
forming a fin over a substrate (method of manufacturing semiconductor device having alternating semiconductor layers 610A, 620A forming fin disposed over substrate 302; Figs. 7, 9 and 15; paragraphs [0041], [0064]), wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked (alternating semiconductor layers 610A, 620A; Figs. 7, 9 and 15; paragraphs [0042], [0064]);
forming a dummy gate structure extending in a first direction and over the fin (dummy gate structures 510A, 510B extending in first direction over fin; Fig. 9; paragraph [0042]);
forming source/drain trenches in the fin and on opposite sides of the dummy gate structures in a second direction different from the first direction (trenches formed in fin stack on opposite sides of structures 510A, 510B in second direction different from first; Fig. 7; paragraph [0038]);
removing the first semiconductor layers through the source/drain trenches (portion of layers 610A removed through trenches to form spacers 710; Fig. 7);
forming a first dielectric layer between the second semiconductor layers and the substrate and forming second dielectric layers between the second semiconductor layers (first dielectric layer defined as first gate dielectric 1502 layer between semiconductor layers 620A and substrate 302, and second dielectric layers defined collectively as second gate dielectric 1502 layers and gate spacer layers 1122, 1124 which are disposed in part between layers 620A; Figs. 9 and 15; paragraphs [0049], [0066]);
forming inner spacers between the second semiconductor layers and the substrate, wherein the first dielectric layer is between the inner spacers in the second direction (inner spacers 710 formed between layers 620A and substrate 302, where first gate dielectric 1502 layer is disposed between inner spacers 710 in second direction; Fig. 15; paragraph [0066]);
forming source/drain features in the source/drain trenches (source/drain structures 910A-910C formed within trenches; Fig. 9; paragraph [0041]); and
replacing the dummy gate structure and the second dielectric layers with a gate structure wrapping around the second semiconductor layers (dummy gate structures 510A, 510B and portion of gate spacer layers 1122, 1124 are replaced with gate structures 1500 wrapping around layers 620A; Fig. 15; paragraphs [0066]-[0067]).
Regarding claim 18, Lin discloses the method of claim 17, further comprising: forming isolation features on opposite sides of the fin in the first direction (isolation structure disposed under bottom surface of source/drain structures 910A-910C on opposite sides of fin 401 in first direction; Fig. 9; paragraph [0042]); and forming hard mask layers over the isolation features, wherein the isolation features and the hard mask layers interface a bottommost first semiconductor layer of the first semiconductor layers (silicon oxide/nitride inner spacer 710 disposed in contact with opposite sides of bottommost layer 610A and above isolation structure; Fig. 9; paragraph [0042]).
Regarding claim 19, Lin discloses the method of claim 17, further comprising: forming dielectric material wrapping around the second semiconductor layers (excess dielectric material from inner spacer 710 deposition wraps around layers 620A; paragraph [0039]); and removing the dielectric material exposed in the source/drain trenches to form the first dielectric layer and the second dielectric layers (excess dielectric material from inner spacer 710 deposition is removed prior to forming first and second dielectric layers; paragraph [0039]).
Regarding claim 21, Lin discloses the method of claim 17, wherein a dimension of the first dielectric layer in the second direction is greater than a dimension of the gate structure in the second direction (dimensions of first dielectric layer in second direction greater than that of gate structure 1500; Fig. 15).
Regarding claim 22, Lin discloses the method of claim 17, wherein a dimension of the first dielectric layer in the second direction is less than a dimension of the gate structure in the second direction (side portion of first dielectric layer interfacing gate metal 1504 has a dimension in the second direction less than that of gate structure 1500; Fig. 15).
Regarding claim 23, Lin discloses a method for manufacturing a semiconductor structure, comprising:
forming a fin extending in a first direction (method of manufacturing semiconductor device having alternating semiconductor layers 610A, 620A forming fin extending in first direction; Figs. 7, 9 and 15; paragraphs [0041], [0064]), wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked (alternating semiconductor layers 610A, 620A; Figs. 7, 9 and 15; paragraphs [0042], [0064]);
forming hard mask layers on opposite sides of a bottommost one of the first semiconductor layers in a second direction different form the first direction (silicon oxide/nitride inner spacer 710 on opposite sides of bottommost layer 610A in second direction different from first direction; Fig. 9; paragraph [0042]);
forming a dummy gate structure over the fin (dummy gate structures 510A, 510B extending in first direction over fin; Fig. 9; paragraph [0042]);
removing the first semiconductor layers (portion of layers 610A removed through trenches to form spacers 710; Fig. 7);
forming a first dielectric layer between the hard mask layers in the second direction and forming second dielectric layers interfacing the dummy gate structure in the second direction (first dielectric layer defined as first gate dielectric 1502 layers disposed between bottommost inner spacers 710 in second direction and second dielectric layers defined collectively as second gate dielectric 1502 layers and ILDs 920 which interface in part with dummy gate structures 510A, 510B in second direction; Figs. 9 and 15);
forming first inner spacers on opposite sides of the first dielectric layer in the first direction and forming second inner spacers on opposite sides of the second dielectric layers in the first direction (first plurality of inner spacers 710 formed on opposite sides of first gate dielectric 1502 layers in first direction and second plurality of inner spacers 710 formed on opposite sides of second gate dielectric 1502 layers in first direction; Fig. 15);
forming source/drain features on opposite sides of the dummy gate structure (source/drain structures 910A-910C formed on opposite sides of the dummy gate structures 510A, 510B; Fig. 9; paragraph [0041]); and
replacing the dummy gate structure with a gate structure over the second semiconductor layers (dummy gate structures 510A, 510B replaced with gate structures 1500 disposed over layers 620A; Fig. 15; paragraphs [0066]-[0067]).
Regarding claim 24, Lin discloses the method of claim 23, wherein bottom surfaces of the hard mask layers are lower than a top surface of the first dielectric layer (bottom surface of the bottommost inner spacer 710 lower than that of top surface of first dielectric layer; Fig. 15).
Regarding claim 25, Lin discloses the method of claim 23, further comprising: forming isolation features on opposite sides of the bottommost one of the first semiconductor layers in the second direction, wherein top surfaces of the isolation features are higher than a bottom surface of the first dielectric layer (isolation structure disposed under bottom surface of source/drain structures 910A-910C on opposite sides of layer 610A in second direction, where top surface of isolation structures are higher than bottom surfaces of first dielectric layer in second direction; Fig. 9; paragraph [0042]).
Regarding claim 26, Lin discloses the method of claim 23, wherein a bottom surface of the gate structure is higher than a bottom surface of a bottommost one of the second semiconductor layers (bottom surface of gate 1500 higher than bottom surface of lowest layer 620A; Fig. 15).
Regarding claim 28, Lin discloses the method of claim 23, wherein a dimension of the first inner spacers in the first direction is greater than a dimension of the second inner spacers in the first direction (inner spacers 710 are concave in shape and therefore one will have dimension in first direction greater than that of another one; Figs. 8A-8B; paragraph [0040]).
Regarding claim 29, Lin discloses the method of claim 23, wherein a dimension of the first inner spacers in the first direction is less than a dimension of the second inner spacers in the first direction (inner spacers 710 are concave in shape and therefore one will have dimension in first direction less than that of another one; Figs. 8A-8B; paragraph [0040]).
Regarding claim 30, Lin discloses a method for manufacturing a semiconductor structure, comprising:
forming a fin extending in a first direction (method of manufacturing semiconductor device having alternating semiconductor layers 610A, 620A forming fin 401 extending in first direction; Figs. 7, 9 and 15; paragraphs [0041], [0064]), wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked (alternating semiconductor layers 610A, 620A; Figs. 7, 9 and 15; paragraphs [0042], [0064]);
forming a dummy gate structure over the fin and extending in a second direction different from the first direction (dummy gate structures 510A, 510B extending over fin in second direction different from first direction; Fig. 9; paragraph [0042]);
forming isolation features on opposite sides of the fin in the second direction (isolation structure disposed under bottom surface of source/drain structures 910A-910C on opposite sides of fin 401 in second direction; Fig. 9; paragraph [0042]);
forming hard mask layers over the isolation features, wherein the hard mask layers interfacing a bottommost one of the first semiconductor layers (hard mask layers defined collectively as silicon oxide/nitride inner spacer 710 and ESLs 630A which are disposed in part in contact with opposite sides of bottommost layer 610A and above isolation structure; Fig. 9; paragraph [0042]);
removing the first semiconductor layers (portion of layers 610A removed through trenches to form spacers 710; Fig. 7);
forming a dielectric layer under a bottommost one of the second semiconductor layers (first gate dielectric 1502 layers disposed in part under bottommost layer 620A; Fig. 15);
forming inner spacers interfacing the dielectric layer in the first direction (first plurality of inner spacers 710 formed on opposite sides of first gate dielectric 1502 layers in first direction; Fig. 15);
forming source/drain features interfacing the second semiconductor layers in the first direction (source/drain structures 910A-910C interfacing layers 620A in first direction; Fig. 9; paragraph [0041]); and
replacing the dummy gate structure with a gate structure (dummy gate structures 510A, 510B replaced with gate structures 1500 disposed over layers 620A; Fig. 15; paragraphs [0066]-[0067]).
Regarding claim 31, Lin discloses the method of claim 30, wherein a thickness of the dielectric layer is in a range from 3 nm to 10 nm (layers 610A, 620A may be between 5 and 20 nm and gate dielectric 1502 layers are shown to occupy only a portion of that thickness; Fig. 15; paragraph [0023]).
Regarding claim 32, Lin discloses the method of claim 30, wherein top surfaces of the hard mask layers are higher than a bottom surface of the bottommost one of the second semiconductor layers (top surfaces of defined hard mask layer higher than bottom surface of bottommost layer 620A; Fig. 15).
Regarding claim 33, Lin discloses the method of claim 30, wherein the dielectric layer comprises concave sidewalls interfacing the inner spacers (gate dielectric 1502 has concave sidewalls matching that of spacers 710; Figs. 8A-8B, 15; paragraph [0040]).
Regarding claim 34, Lin discloses the method of claim 30, wherein sidewalls of the dielectric layer are offset from sidewalls of the gate structure in the first direction (concave sidewalls of gate dielectric 1502 are offset in first direction from that of gate structure 1500; Fig. 15).
Regarding claim 36, Lin discloses the method of claim 30, wherein the inner spacers comprise concave sidewalls facing the dielectric layer (gate dielectric 1502 has concave sidewalls matching that of spacers 710; Figs. 8A-8B, 15; paragraph [0040]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20, 27 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of US 2021/0343639 A1 to Wang et al. (hereinafter “Wang”).
Regarding claim 20, Lin discloses the method of claim 17. Lin fails to disclose further comprising: forming a back-side via passing through the substrate and electrically connected to one of the source/drain features, wherein the back-side via interfaces the first dielectric layer.
However, Wang discloses forming a back-side via passing through the substrate and electrically connected to one of the source/drain features, wherein the back-side via interfaces the first dielectric layer (backside via 300 passing through substrate 110 and space where substrate portion 112 was removed and electrically connected to source/drain 190S and interfacing dielectric layer 270 and dielectric via spacer 290; Fig. 24A; paragraphs [0088]-[0089]).
Lin and Wang are both considered to be analogous to the claimed invention because they are in the same field of gate all around transistors. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of Wang in order to potentially provide enhanced routing and scaling due to shortened power path and reduced frontside metal usage and enhanced electrical performance due to lower source resistance and contact resistance when the via lands on a high-quality S/D surface.
Regarding claim 27, Lin discloses the method of claim 23. Lin fails to disclose further comprising: forming a via interfacing bottom surfaces of the dielectric layer and one of the source/drain features
However, Wang discloses forming a via interfacing bottom surfaces of the dielectric layer and one of the source/drain features (backside via 300 interfacing bottom surfaces of dielectric layer 270, dielectric via spacer 290 and source/drain 190S; Fig. 24A; paragraphs [0088]-[0089]).
Lin and Wang are both considered to be analogous to the claimed invention because they are in the same field of gate all around transistors. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of Wang in order to potentially provide enhanced routing and scaling due to shortened power path and reduced frontside metal usage and enhanced electrical performance due to lower source resistance and contact resistance when the via lands on a high-quality S/D surface.
Regarding claim 35, Lin discloses the method of claim 30. Lin fails to disclose further comprising: forming a via interfacing sidewalls of the dielectric layer and one of the source/drain features.
However, Wang discloses forming a via interfacing sidewalls of the dielectric layer and one of the source/drain features (backside via 300 interfacing sidewalls of dielectric layer 270 and dielectric via spacer 290 and one of source/drain 190S; Fig. 24A; paragraphs [0088]-[0089]).
Lin and Wang are both considered to be analogous to the claimed invention because they are in the same field of gate all around transistors. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of Wang in order to potentially provide enhanced routing and scaling due to shortened power path and reduced frontside metal usage and enhanced electrical performance due to lower source resistance and contact resistance when the via lands on a high-quality S/D surface.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2023/0067804 A1 to Shen et al., US 10,797,163 B1 to Yu et al. and US 2020/0381251 A1 to Kim et al. disclose related GAA structures with similar structural orientation relationships.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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