Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, Embodiment of Fig. 7 (claims 16-35) in the reply filed on 06/16/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/01/2024 and 03/31/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 26, 28 and 31-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 26 recites the limitation "the bottom surface" in claim 26. There is insufficient antecedent basis for this limitation in the claim. It is unclear as “the bottom surface” of which element applicant refers.
Claim 31 recites the limitation " the epitaxial source/drain region" in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Reznicek (US 10,170,638).
As for claim 16, Reznicek disclose in Figs. 1-7 and the related text a method comprising:
forming a semiconductor fin on a top surface of a semiconductor substrate 10, wherein the semiconductor fin 12L/14L comprises first semiconductor layers 12L and second semiconductor layers 14L alternately arranged (Figs. 1-2);
forming a source/drain recess CS through the semiconductor fin and into the semiconductor substrate (fig. 3);
recessing the first semiconductor layers to form inner spacer cavities (fig. 4, col. 7 lines 26-29);
forming inner spacers 20S in the inner spacer cavities, wherein the inner spacers include a bottom inner spacer 20S/20L disposed between the top surface of the semiconductor substate 10 and a bottommost second semiconductor layer 14P (Fig. 6);
extending bottom inner spacer 20S/20L towards the source/drain recess (Fig. 4); and
growing an epitaxial source/drain region 26 from the second semiconductor layers 14P (fig. 7, Col. 8 lines 31-45).
Claims 16-17, 19-20 and 31-35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 2022/0336612).
As for claim 16, Chang et al. disclose in Figs. 2A-2Q and the related text a method comprising:
forming a semiconductor fin on a top surface of a semiconductor substrate 102 (Fig. 2A), wherein the semiconductor fin comprises first semiconductor layers 119/120 and second semiconductor layers 105/107 alternately arranged;
forming a source/drain recess 140 through the semiconductor fin and into the semiconductor substrate (Fig. 2B, [0048]);
recessing the first semiconductor layers 120 to form inner spacer cavities [0049];
forming inner spacers 148/112 in the inner spacer cavities, wherein the inner spacers include a bottom inner spacer 112 disposed between the top surface of the semiconductor substate 102 and a bottommost second semiconductor layer 107 (fig. 2H, [0056]-[0057]);
extending bottom inner spacer 112 towards the source/drain recess (Fig. 2I); and
growing an epitaxial source/drain region 110 from the second semiconductor layers (Fig. 2J, [0068]).
As for claim 17, Chang et al. disclose the method of claim 16, further comprising: prior to extending the bottom inner spacer, growing a bottom epitaxial layer 152 in the recess (Fig. 2D, [0051]), wherein an extended portion of the bottom inner spacer 112 is formed over the bottom epitaxial layer (Fig. 2I).
As for claim 19, Chang et al. disclose the method of claim 16, wherein extending the bottom inner spacer 112 comprises: forming a tapered portion on a sidewall of the bottom inner spacer 112 (Fig. 2M).
As for claim 20, Chang et al. disclose the method of claim 16, further comprising: forming a backside source/drain contact feature 166, wherein the backside source/drain contact feature 166 is in (electrically/thermally) contact with the extended portion of the bottom inner spacer (Fig. 2I).
As for claim 31, Chang et al. disclose in Figs. 2A-2Q and the related text a method, comprising:
forming two or more semiconductor channel layers 107/120 vertically stacked above a top surface of the semiconductor substrate 102;
forming two or more inner spacers 148/112 disposed alternately stacked with the two or more semiconductor channel layers, wherein the two or more inner spacers 148/112 include a bottom inner spacer 148/112, wherein the bottom inner spacer comprises: a main portion 148 disposed between a bottommost semiconductor channel layer 107 and the top surface of the semiconductor substrate 102 (fig. 2H); and
an extended portion 112 extending from a sidewall of the main portion (Fig. 2H), wherein the extended portion 112 extends beyond the two or more semiconductor channel layers and under a bottom surface of the epitaxial source/drain region 110, and
growing an epitaxial source/drain region 110 from the two or more semiconductor channel layers (Fig. 2J, [0068]).
As for claim 32, Chang et al. disclose the method of claim 31, wherein the extended portion 112 includes:
a proximal (side) end in contact with the sidewall of the main portion; and
a distal (middle) end away from the main portion, and the extended portion tapers from the proximal end to the distal end.
As for claim 33, Chang et al. disclose the method of claim 31, wherein the main portion 148 and the extended portion 112 (156) are formed from the same material ([0050]-[0051]).
As for claim 34, Chang et al. disclose the method of claim 31, wherein the main portion 148 and the extended portion 112 (156) are formed from different materials ([0050]-[0051]).
As for claim 35, Chang et al. disclose the method of claim 31, further comprises growing a bottom epitaxial layer 152 prior to forming the extended portion of the bottom inner spacer 112 (Fig. 2E, [0051]).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21 rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Chu et al. (US 2022/0069135).
As for claim 21, Reznicek discloses in Figs. 1-8 and the related text a method comprising:
a forming two or more semiconductor channel layers 12P/14P stacked over a top surface of a semiconductor substrate 10;
forming inner spacers 20S between the two or more semiconductor channel layers 14P;
extending a bottom inner spacer lower 20S/20L disposed between a bottommost semiconductor channel layer 14P and the top surface of the semiconductor substrate 10 (Fig. 7); and
forming an epitaxial source/drain region 26 connected to the two or more semiconductor channel layers 14P.
the epitaxial source/drain region includes a first epitaxial layer and a second epitaxial layer disposed over the first epitaxial layer.
Reznicek does not disclose the epitaxial source/drain region includes a first epitaxial layer and a second epitaxial layer disposed over the first epitaxial layer.
Chu et al. teach in Fig. 12A-13A and the related text an epitaxial source/drain region includes a first epitaxial layer 236B and a second epitaxial layer 138 disposed over the first epitaxial layer (Fig. 13A, [0030]).
Chu et al. and Reznicek are analogous art because they both are directed transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Reznicek because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Reznicek to include the limitations as taught by Chu et al., in order to reduce resistance and improve performance of the transistor (Chu et al. ¶0004).
Claims 18, 21-27 and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. in view of Chu et al..
As for claim 18, Chang et al. disclose the method of claim 17, wherein a portion of the bottom epitaxial layer 152 is exposed to the source/drain recess (Fig. 2L).
Chang et al. do not disclose a portion of the epitaxial source/drain region is grown from the bottom epitaxial layer.
Chu et al. teach in Fig. 12A-13A and the related text a portion of the epitaxial source/drain region 238 is grown from the bottom epitaxial layer 236B (Fig. 13A, [0030]).
Chang et al. and Chu et al. are analogous art because they both are directed transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chang et al. to include the limitations as taught by Chu et al., in order to reduce resistance and improve performance of the transistor (Chu et al. ¶0004).
As for claim 21, Chang et al. disclose in Figs. 2A-2Q and the related text a method, comprising:
forming two or more semiconductor channel layers 107/120 stacked over a top surface of a semiconductor substrate 102 (Fig. 2A-2B, [0037]);
forming inner spacers 148 between the two or more semiconductor channel layers (Fig. 2C);
extending a bottom inner spacer 112 disposed between a bottommost semiconductor channel layer and the top surface of the semiconductor substrate (Fig. 2H); and
forming an epitaxial source/drain region 110 connected to the two or more semiconductor channel layers 107/120.
Chang et al. do not disclose the epitaxial source/drain region includes a first epitaxial layer and a second epitaxial layer disposed over the first epitaxial layer.
Chu et al. teach in Fig. 12A-13A and the related text an epitaxial source/drain region includes a first epitaxial layer 236B and a second epitaxial layer 138 disposed over the first epitaxial layer (Fig. 13A).
Chang et al. and Chu et al. are analogous art because they both are directed transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chang et al. to include the limitations as taught by Chu et al., in order to reduce resistance and improve performance of the transistor (Chu et al. ¶0004).
As for claim 22, Chang et al. disclose the method of claim 21, further comprising: forming a bottom epitaxial layer 152 prior to extending the bottom inner spacer (Fig. 2D-2H), wherein the bottom inner spacer 112 is in contact with the top surface of the semiconductor substrate and the bottom epitaxial layer (Fig. 2H).
As for claim 23, Chang et al. disclose the method of claim 22, wherein the bottom inner spacer 112 includes: a top surface in contact with the bottommost semiconductor channel layer 107; and a bottom surface in (electrically/thermally) contact with the top surface of the semiconductor substrate and the bottom epitaxial layer (Fig. 2H-2I).
As for claim 24, Chang et al. disclose the method of claim 23, wherein (any portion of) the bottom inner spacer 112 has a first width at the top surface and a second width at the bottom surface, and the second width is greater than the first width.
As for claim 25, Chang et al. disclose the method of claim 22, wherein the bottom surface of the bottom inner spacer 112 is a planar surface (Fig. 2H-2I).
As for claim 26, Chang et al. disclose the method of claim 22, wherein the bottom surface includes a planar portion (portion on top of 152) and a sloped portion (portion on side of 152) (Fig. 2I).
As for claim 27, Chang et al. disclose the method of claim 26, wherein the sloped portion extends below the top surface of the semiconductor substrate (Fig. 2I).
As for claim 29, Chang et al. disclose the method of claim 21, wherein the bottom inner spacer 112 comprises: a main portion 148 disposed between the bottommost semiconductor channel layer 107 and a top surface of the semiconductor substrate 102 (Fig. 2I-2H); and an extended portion 112 extending from a sidewall of the main portion (Fig. 2I), wherein the extended portion 112 is disposed between the epitaxial source/drain region 110 and the bottom epitaxial layer 152 (Fig. 2H-2I).
As for claim 30, Chang et al. disclose the method of claim 29, wherein the extended portion has a proximal end in contact with the main portion and a distal end away from the main portion, and the extended portion tapers from the proximal end to the distal end (Fig. 2I).
Claims 28 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. in view of Reznicek.
As for claim 28, Chang et al. disclose the method of claim 26, except the sloped portion extends above the top surface of the semiconductor substrate.
Reznicek teaches in Fig. 7 and the related text a sloped portion (bottom portion of 24) extends above the top surface of the semiconductor substrate 10.
Chang et al. and Reznicek are analogous art because they both are directed transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chang et al. to include the limitations as taught by Rezicek in order to achieved the device properties.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/ Primary Examiner, Art Unit 2811
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