DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou et al. (US 9899267) in view of Tung (US 20180211960).
Regarding claim 1, Liou discloses that a semiconductor device, comprising:
a semiconductor fin 10F (Fig. 5) extending along a first direction above a substrate 10;
a gate structure 30 (Fig. 5-6) extending across the semiconductor fin 10F along a second direction perpendicular to the first direction (a vertical direction is a first direction and a horizontal direction is a second direction in Fig. 5, which is a perpendicular to each other); and
a dielectric isolation plug 61(60) extending downwardly from a top surface of a fin into a bottom of the fin (Fig. 8-13).
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Liou fails to specify that the semiconductor fin comprising a silicon germanium layer and a silicon layer over the silicon germanium layer.
However, Tung suggests that that the semiconductor fin comprising a silicon germanium layer and a silicon layer over the silicon germanium layer (Fig. 5, para. 0023, note: a top portion 34 can be a silicon and a bottom portion 34 can be a SiGe).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Liou with the semiconductor fin comprising a silicon germanium layer and a silicon layer over the silicon germanium layer as taught by Tung in order to enhance a variation of semiconductor Fin materials and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, Liou & Tung disclose that the dielectric isolation plug further extends downwardly to a bottom surface of the silicon germanium layer 36 (Tung, para. 0023, a SiGe).
Reclaim 3, Liou & Tung disclose that the dielectric isolation plug 60 has a width decreasing as a distance from the substrate decreases when viewed in a cross section taken along the first direction (Liou, Fig. 8-13).
Reclaim 4, Liou & Tung disclose that when viewed in a cross section taken along the first direction, a maximum width of a portion of the dielectric isolation plug in the silicon layer is greater than a maximum width of a portion of the dielectric isolation plug in the silicon germanium layer (Liou, Fig. 8-13).
Reclaim 5, Liou & Tung disclose that when viewed in a cross section taken along the second direction, the gate structure wraps around three sides of an upper part of the dielectric isolation plug (Liou, Fig. 8-13).
Reclaim 6, Liou & Tung disclose that a shallow trench isolation (STI) region 20 around a lower part of the dielectric isolation plug 62(60) when viewed in the cross section taken along the second direction (Liou, Fig.7 & 8).
Reclaim 7, Liou & Tung disclose that an interface between the dielectric isolation plug and the STI region 20 is coterminous with an interface between the dielectric isolation plug and the gate structure (Liou, Fig. 7-8).
Reclaim 8, Liou & Tung disclose that the dielectric isolation plug has a bottom end substantially level with a bottom surface of the STI region 20 when viewed in the cross section taken along the second direction (Liou, Fig. 7-8).
Reclaim 9, Liou & Tung disclose that the gate structure 30E comprises a gate dielectric layer in contact with three sides of the dielectric isolation plug when viewed along a cross section taken along the second direction (Liou, Fig. 7-8).
Reclaim 10, Liou & Tung disclose that when viewed in a cross section taken along the first direction, the dielectric isolation plug and the gate structure form an interface substantially level with the top surface of the silicon layer of the semiconductor fin (Liou, Fig. 7-8).
Reclaim 11, Liou & Tung disclose that gate spacer 39 on a sidewall of the gate structure 30E, the gate spacer forms an interface with the dielectric isolation plug at a position lower than the top surface of the silicon layer of the semiconductor fin (Liou, Fig. 7-8).
Reclaim 12, Liou & Tung disclose that the interface formed between the gate spacer and the dielectric isolation plug has a concave shape when viewed in a cross section taken along the first direction (Liou, Fig. 7).
Regarding claim 13, Liou & Tung disclose that a semiconductor device, comprising:
a substrate 10;
a first semiconductor fin 10F extending along a first direction above the substrate, the first semiconductor fin comprising a first silicon germanium layer and a first silicon layer over the first silicon germanium layer (Tung, para. 0023);
a first gate structure 30E extending across the first semiconductor fin along a second direction perpendicular to the first direction; a second semiconductor fin extending along the first direction above the substrate and aligned with the first semiconductor fin along the first direction; a second gate structure extending across the second semiconductor fin along the second direction perpendicular to the first direction; and
a dielectric isolation plug 62(60) between the first and second semiconductor fins, wherein the dielectric isolation plug is in contact with the first silicon germanium layer of the first semiconductor fin (Fig. 7 in view of Tung’s Fig. 5. Para. 0023).
Reclaim 14, Liou & Tung disclose that the second semiconductor fin comprises a second silicon germanium layer and a second silicon layer over the second silicon germanium layer, and the dielectric isolation plug is in contact with the second silicon germanium layer of the second semiconductor fin.
Reclaim 15, Liou & Tung disclose that a bottom surface of the dielectric isolation plug is in contact with the substrate.
Reclaim 16, Liou & Tung disclose that a third gate structure extending across the dielectric isolation plug along the second direction.
Regarding claim 17, Liou & Tung disclose that a semiconductor device, comprising:
a substrate 10 (Fig. 7-8, Liou);
a first semiconductor fin 10F (Fig. 7-8, Liou) extending along a first direction above the substrate, the first semiconductor fin comprising a first silicon germanium layer and a first silicon layer over the first silicon germanium layer (Tung, para. 0023);
a first gate structure 30E extending across the first semiconductor fin along a second direction perpendicular to the first direction (Liou, Fig. 7); and
a first dielectric isolation plug 62(60) at a longitudinal end of the first semiconductor fin, wherein the first dielectric isolation plug has a top surface in contact with the first gate structure and a bottom surface below the first silicon germanium layer of the first semiconductor fin (Liou’s Fig. 8-12 in view of Tung’s Fig. 5).
Reclaim 18, Liou & Tung disclose that a bottom surface of the first gate structure extends beyond opposite sides of the first dielectric isolation plug (Liou’s Fig. 8-12 in view of Tung’s Fig. 5).
Reclaim 19, Liou & Tung disclose that a second semiconductor fin extending along the first direction above the substrate and misaligned with the first semiconductor fin along the first direction; and a second gate structure extending across the second semiconductor fin and the first dielectric isolation plug (Liou’s Fig. 8-12 in view of Tung’s Fig. 5).
Reclaim 20, Liou & Tung disclose that a second dielectric isolation plug at a longitudinal end of the second semiconductor fin, wherein the first gate structure extends across the second dielectric isolation plug (Liou’s Fig. 8-12 in view of Tung’s Fig. 5).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10497778 in view of Liou et al. (US 9899267) and further in view of Tung (US 20180211960).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over 1-20 claims of U.S. Patent No. 11948970 in view of Liou et al. (US 9899267) and further in view of Tung (US 20180211960).
Conclusion
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/SU C KIM/Primary Examiner, Art Unit 2899