DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 & 5-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20160336315) in view of Tung (US 20180211960).
Regarding claim 1, You discloses that a semiconductor device, comprising:
a semiconductor fin 110 extending along a first direction above a substrate 100;
a gate structure 150 extending across the semiconductor fin along a second direction perpendicular to the first direction (Fig. 2); and
a dielectric isolation plug 106 extending downwardly from a top surface of the fin to bottom (Fig. 2 & 5) of the fin, wherein the gate structure 160, 170, 165 covers a top surface of the dielectric isolation plug 107.
Maeda fails to specify that a semiconductor fin comprising a silicon germanium layer and a silicon layer over the silicon germanium layer.
However, Tung suggests that that the semiconductor fin comprising a silicon germanium layer and a silicon layer over the silicon germanium layer (Fig. 5, para. 0023, note: a top portion 34 can be a silicon and a bottom portion 34 can be a SiGe).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide You with the semiconductor fin comprising a silicon germanium layer and a silicon layer over the silicon germanium layer as taught by Tung in order to enhance a variation of semiconductor Fin materials and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, You & Tung disclose that the dielectric isolation plug further extends downwardly to a bottom surface of the silicon germanium layer (Maeda in view of Tung, Tung suggests that a top portion can be silicon and a bottom portion can be a SiGe).
Reclaim 5, You & Tung disclose that when viewed in a cross section taken along the second direction, the gate structure 150 wraps around three sides of an upper part of the dielectric isolation plug 106 (You, Fig. 5).
Reclaim 6, You & Tung disclose that a shallow trench isolation (STI) region 107 around a lower part of the dielectric isolation plug 106 when viewed in the cross section taken along the second direction (You, Fig. 3).
Reclaim 7, You & Tung disclose that an interface between the dielectric isolation plug and the STI region is coterminous with an interface between the dielectric isolation plug and the gate structure (You, Fig. 3 & 5).
Reclaim 8, You & Tung disclose that the dielectric isolation plug has a bottom end substantially level with a bottom surface of the STI region when viewed in the cross section taken along the second direction (You, Fig. 3).
Reclaim 9, You & Tung disclose that the gate structure 150 comprises a gate dielectric layer 165 & 155 in contact with three sides of the dielectric isolation plug when viewed along a cross section taken along the second direction (You, Fig. 5).
Reclaim 10, You & Tung disclose that when viewed in a cross section taken along the first direction, the dielectric isolation plug and the gate structure form an interface substantially level with the top surface of the silicon layer of the semiconductor fin (You, Fig. 3).
Reclaim 11, You & Tung disclose that a gate spacer on a sidewall of the gate structure, the gate spacer 165 forms an interface with the dielectric isolation plug 160 at a position lower than the top surface of the silicon layer of the semiconductor fin (Fig. 5, You).
Reclaim 12, You & Tung disclose that the interface formed between the gate spacer and the dielectric isolation plug has a concave shape when viewed in a cross section taken along the first direction (Fig. 5).
Regarding claim 13, You & Tung disclose that a semiconductor device, comprising:
a substrate 100;
a first semiconductor fin 110 extending along a first direction above the substrate 100 (Fig. 8, You), the first semiconductor fin comprising a first silicon germanium layer and a first silicon layer over the first silicon germanium layer (Tung, para 0023);
a first gate structure 120 extending across the first semiconductor fin along a second direction perpendicular to the first direction (You, Fig. 3);
a second semiconductor fin 210 extending along the first direction above the substrate and aligned with the first semiconductor fin along the first direction (You, Fig. 5 & 8);
a second gate structure 220 extending across the second semiconductor fin along the second direction perpendicular to the first direction (You, Fig. 5 & 8);
a dielectric isolation plug 106 between the first and second semiconductor fins, wherein the dielectric isolation plug is in contact with the first silicon germanium layer of the first semiconductor fin; and
a third gate structure 150 vertically overlapping the dielectric isolation plug (You, Fig. 5 & 8).
Reclaim 14, You & Tung disclose that the second semiconductor fin comprises a second silicon germanium layer and a second silicon layer over the second silicon germanium layer, and the dielectric isolation plug is in contact with the second silicon germanium layer of the second semiconductor fin (You, Fig. 5 & 8 in view of Tung’s para. 0023).
Reclaim 15, You & Tung disclose that a bottom surface of the dielectric isolation plug is in contact with the substrate 100 (You, Fig. 7).
Reclaim 16, You & Tung disclose that wherein the third gate structure extends across the dielectric isolation plug along the second direction (Fig. 8, You).
Regarding claim 17, You & Tung disclose that a semiconductor device, comprising:
a substrate 100 (You, Fig. 5);
a first semiconductor fin 110 extending along a first direction above the substrate, the first semiconductor fin comprising a first silicon germanium layer and a first silicon layer over the first silicon germanium layer (Tung, para. 0023);
a first gate structure 220 extending across the first semiconductor fin along a second direction perpendicular to the first direction (You, Fig. 8); and
a first dielectric isolation plug 106 at a longitudinal end of the first semiconductor fin, wherein the first dielectric isolation plug has a top surface in contact with the first gate structure and a bottom surface below the first silicon germanium layer of the first semiconductor fin, wherein the top surface of the first dielectric isolation plug is covered by the first gate structure (You’s Fig. 5 & 8).
Reclaim 18, You & Tung disclose that a bottom surface of the first gate structure extends beyond opposite sides of the first dielectric isolation plug (You, Fig. 5 & 8).
Reclaim 19, You & Tung disclose that a second semiconductor fin extending along the first direction above the substrate and misaligned with the first semiconductor fin along the first direction; and a second gate structure extending across the second semiconductor fin and the first dielectric isolation plug (You, Fig. 5 &8).
Reclaim 20, You & Tung disclose that a second dielectric isolation plug at a longitudinal end of the second semiconductor fin, wherein the first gate structure extends across the second dielectric isolation plug (Fig. 8).
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20160336315) in view of Tung (US 20180211960) and further in view of Chang et al. (US -).
Reclaim 3, Maeda & Tung fail to teach that that the dielectric isolation plug has a width decreasing as a distance from the substrate decreases when viewed in a cross section taken along the first direction.
However, Chang suggests that the dielectric isolation plug has a width decreasing as a distance from the substrate decreases when viewed in a cross section taken along the first direction (Fig. 1I)
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide A with XX as taught by B in order to enhance quality and the reliability of the metal gate stack layer (para. 0058) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 4, Maeda, Tung, & Chang disclose that when viewed in a cross section taken along the first direction, a maximum width of a portion of the dielectric isolation plug in the silicon layer is greater than a maximum width of a portion of the dielectric isolation plug in the silicon germanium layer (Tung in view of Chang’s Fig. 1I).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SU C KIM/ Primary Examiner, Art Unit 2899
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