Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 recites “wherein a minimum distance between a gate structure of the electronic fuse and a gate structure of the switching transistor is smaller than 100 nm.” The word “minimum” in this context does not provide a clear boundary to the claim, does applicant mean “a distance at the point where a gate structure of the electronic fuse and a gate structure of the switching transistor are closest together, is smaller than 100 nm”? Or simply that “a distance” … is smaller than 100 nm?
For purposes of compact prosecution, Claim 11 will be interpreted to instead recite “wherein a
Appropriate correction is required
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (“Lin”), US 2011/0147853, in view of Lee US 2001/0017800.
Regarding Claim 1, Lin discloses a semiconductor device (Fig. 8; ¶ 0015), comprising:
a substrate (112; Fig. 8; ¶ 0017 “substrate 112”);
an electronic fuse (168; Fig. 8; ¶ 0030 “e-fuse 168”) on the substrate (Fig. 8); and
a switching transistor (116b; Fig. 8; ¶ 0030 “MOS transistors 166b”) on the substrate (Fig. 8) and next to the electronic fuse (Fig. 8).
Lin does not disclose wherein:
a first doping region of the substrate underneath the electronic fuse has a first conductive type, a second doping region of the substrate underneath the switching transistor has a second conductive type, and the first conductive type and the second conductive type are the same, and;
the first doping region of the substrate is disposed between third doping regions of the substrate, and third conductive types of the third doping regions are different from the first conductive type.
Lee discloses wherein:
a first doping region (55p; right side of Fig. 13A; ¶ 0039 “P-well region 55p…formed on the semiconductor substrate 51 underlying the isolation layers 53”) of the substrate (51; right side of Fig. 13A; ¶ 0039 “semiconductor substrate 51”) underneath the electronic fuse (right side of Fig. 13A; ¶ 0039 “an isolation layer 53 defining an active region is provided on a predetermined region of a semiconductor substrate 51” and “isolation layer 53 is formed using a…trench isolation process” in this instance a first doping region 55p of the substrate 51 is underneath an isolation region 53 and the electronic fuse of Lin is over an isolation region, therefore the first doping region 55p is underneath the electronic fuse) has a first conductive type (p-type; right side of Fig. 13A; ¶ 0039 “P-well region 55p”), a second doping region (55p; right side of FIG. 13A; ¶ 0039 “P-well region 55p formed on the semiconductor substrate 51”) of the substrate underneath (right side of FIG. 13A) the switching transistor (NMOS transistor of the right side of FIG. 13A; ¶ 0041 “operating as…an NMOS transistor”) has a second conductive type (p-type; right side of Fig. 13A; ¶ 0039 “P-well region 55p”), and the first conductive type and the second conductive type are the same (both are p-type), and;
the first doping region of the substrate is disposed between (right side of Fig. 13A; first doping region 55p is between third doping regions 79 and 55n) third doping regions (79, 55n; right side of Fig. 13A; ¶ 0039 “N-well region 55n”; ¶ 0048 “N-type source/drain regions 79”) of the substrate, and third conductive types (n-type; right side of Fig. 13A; ¶ 0039 “N-well region 55n”; ¶ 0048 “N-type source/drain regions 79”) of the third doping regions are different from (n-type is different from p-type) the first conductive type.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lin to have wherein a first doping region of the substrate underneath the electronic fuse has a first conductive type, a second doping region of the substrate underneath the switching transistor has a second conductive type, and the first conductive type and the second conductive type are the same, and; the first doping region of the substrate is disposed between third doping regions of the substrate, and third conductive types of the third doping regions are different from the first conductive type, as taught by Lee, because a doped substrate under transistors improves conductivity, speed, stability, and manufacturability, while enabling precise control over device behavior, plus a doped substrate under an insulation region that is located under an electronic fuse improves electrical performance, reduces parasites, enhances reliability, and supports advanced device scaling.
Regarding Claim 8, Lin discloses wherein the electronic fuse comprises a gate structure (122, 126, 165; Fig. 8; ¶ 0020 “work function metal layer 126 over the gate dielectric layer 122”; ¶ 0030 “gate dielectric layer 122” and “metal conductive structures 165”), first spacers (136; Figs. 3, 8; ¶ 0022 “offset spacers 134” and “spacer structures may include the silicon oxide layer 136, the silicon nitride cap layer 138 and the second silicon oxide layer 140”) on sidewalls of the gate structure (Fig. 8), and second spacers (138; Figs. 3, 8; ¶ 0022 “offset spacers 134” and “spacer structures may include the silicon oxide layer 136, the silicon nitride cap layer 138 and the second silicon oxide layer 140”) on the first spacers (Figs. 3, 8).
Regarding Claim 10; Lin does not specifically disclose wherein:
the first conductive type is a P type, the second conductive type is a P type, and the third conductive types are N types; or the first conductive type is an N type, the second conductive type is an N type, and the third conductive types are P types.
Lee discloses wherein:
the first conductive type is a P type (right side of Fig 13A; ¶ 0039 “P-well region 55p”), the second conductive type is a P type (right side of Fig. 13A; ¶ 0039 “P-well region 55p”), and the third conductive types are N types (right side of Fig. 13A; ¶ 0039 “N-well region 55n”; ¶ 0048 “N-type source/drain regions 79”); or the first conductive type is an N type, the second conductive type is an N type, and the third conductive types are P types.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lin to have wherein: the first conductive type is a P type, the second conductive type is a P type, and the third conductive types are N types; or the first conductive type is an N type, the second conductive type is an N type, and the third conductive types are P types, as taught by Lee, because a doped substrate under transistors improves conductivity, speed, stability, and manufacturability, while enabling precise control over device behavior, plus a doped substrate under an insulation region that is located under an electronic fuse improves electrical performance, reduces parasites, enhances reliability, and supports advanced device scaling.
Regarding Claim 11, Lin does not disclose wherein a minimum distance between a gate structure of the electronic fuse and a gate structure of the switching transistor is smaller than 100 nm.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lin to have wherein a minimum distance between a gate structure 165 of the electronic fuse 168 and a gate structure 165 of the switching transistor 166b is smaller than 100 nm, because making the semiconductor device more compact increases the speed of electrical signals between the electronic fuse and switching transistor (thereby improving the performance of the semiconductor device), lowers manufacturing costs, and lowers the overall power consumption of the semiconductor device.
Allowable Subject Matter
Claims 2-7, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, the prior art does not teach or render obvious wherein the first doping region and the third doping regions are disposed between source/drain doping regions of the substrate. Therefore, the combination of Claims 1 and 2 is considered allowable.
Claims 3-6 incorporate all of the limitations of allowable Claim 2. Therefore, they are also allowable.
Regarding Claim 7, the prior art does not teach or render obvious wherein the first doping region is in direct contact with the third doping regions. Therefore, the combination of Clams 1 and 7 is considered allowable.
Regarding Claim 9, the prior art does not teach or render obvious wherein the first doping region is in direct contact with the third doping regions. Therefore, the combination of Claims 1, 8, and 9 is considered allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chung et al. US 2010/0059823, Lin et al. US 2012/0228718, Guo et al. US 2007/0246796, and Lin et al. 2012/0225524 disclose a semiconductor device having a substrate, an electronic fuse, and a transistor.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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