Prosecution Insights
Last updated: August 17, 2026
Application No. 18/593,971

EMBEDDED MEMORY DEVICE AND FABRICATION METHOD THEREOF

Non-Final OA §112
Filed
Mar 03, 2024
Priority
Jan 30, 2024 — CN 202410129188.3
Examiner
DAS, PINAKI
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
41 granted / 46 resolved
+21.1% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
37 currently pending
Career history
88
Total Applications
across all art units

Statute-Specific Performance

§103
48.0%
+8.0% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 46 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I and Claims 1-10 in the reply filed on 5/26/2026 is acknowledged. Claims 11-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/26/2026. Information Disclosure Statement Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 1 recites the limitation wherein, “a plurality of data storage structures respectively disposed on the plurality of conductive vias”. A data storage structure can be any memory storage structure like MRAM, DRAM, ferromagnetic-RAM, NAND and many others well-known in the semiconductor industry. However, only details of a MRAM storage device comprising a magnetic tunnel junction (MTJ) structure and it’s method of manufacturing are shown in the drawings, and drawings showing the implementation of other data storage structures are missing. Therefore, the features recited in the claim must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-10 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites the limitation wherein “a plurality of data storage structures respectively disposed on the plurality of conductive vias”, in lines 6-7. A data storage structure can be any memory storage structure like MRAM, DRAM, ferromagnetic-RAM, NAND and many others well-known in the semiconductor industry. However, only details of a MRAM storage device comprising a magnetic tunnel junction (MTJ) structure and it’s method of manufacturing are provided in the original specification. Manufacturing or details of how other data storage structures can be implemented as encompassed by the claim are not provided in the original application, and hence the claim is rejected. Claims 2-10 depend from claim 1 and inherit the same issues and therefore rejected. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Mar 03, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707948
CONDUCTIVE VIA STRUCTURES FOR GATE CONTACT OR TRENCH CONTACT
5y 2m to grant Granted Aug 11, 2026
Patent 12707678
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
3y 7m to grant Granted Aug 11, 2026
Patent 12702043
HIGH-DENSITY MICROBUMP ARRAYS WITH ENHANCED ADHESION AND METHODS OF FORMING THE SAME
4y 2m to grant Granted Aug 04, 2026
Patent 12677451
BOTTOM DIELECTRIC ISOLATION FOR VERTICALLY STACKED DEVICES
4y 3m to grant Granted Jul 07, 2026
Patent 12677441
SEMICONDUCTOR DEVICE
4y 0m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.7%)
3y 6m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 46 resolved cases by this examiner. Grant probability derived from career allowance rate.

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