Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on July 21, 2026, regarding the application filed March 4, 2024.
Election/Restrictions
Applicant’s election without traverse of Invention I, corresponding to claims 1-15, in the reply filed on July 21, 2026 is acknowledged. Claims 16-21 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-21 are pending, with claims 16-21 currently withdrawn from consideration.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on China application serial no. 202310007343.X, filed on January 4, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings filed with the application on March 4, 2024 are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Karhade et al., US 2021/0391295 A1 (hereinafter Karhade) in view of Deshpande et al., US 2016/0343666 A1 (hereinafter Deshpande).
Regarding claim 1, Karhade discloses: A bridge chip (Karhade, FIG. 46, bridge component 110, [0030]), wherein a top surface of the bridge chip (Karhade, FIG. 46, top surface of bridge component 110) is provided with a plurality of first pads (Karhade, FIG. 46, conductive contacts 118, [0030]) and a chip connecting structure (Karhade, FIG. 46, plurality of high-temperature solder 168, [0064]), (Karhade, FIG. 46 shows conductive contacts 180 of N-1 metal layer [the first metal wire layer] connected to bottom surface of bridge component 110 [the bridge chip], [0072]), and the chip connecting structure is configured to bridge at least two chips (Karhade, FIG. 46 shows plurality of high-temperature solder 168 [the chip connecting structure] on top surface of bridge component 110 [the bridge chip] configured to bridge microelectronic components 130-1 and 130-2 [at least two chips], [0032-0033]).
Karhade is silent regarding: the plurality of first pads are separately configured to connect a lead, the lead is configured to electrically connect the top surface of the bridge chip.
However, Deshpande, in the same field of endeavor, teaches: the plurality of first pads (Deshpande, FIG. 1, 2F, bond pads 158, [0017], analogous to the conductive contacts 118 of Karhade) are separately configured to connect a lead (Deshpande, FIG. 1, 2F, show bridge second surface bond pads 158 [the plurality of first pads] separately connected to conductive via 160 [the lead], [0017]), the lead is configured to electrically connect the top surface of the bridge chip (Deshpande, FIG. 1, 2F, “each of the plurality of through-bridge conductive vias 160 [the leads] extends [electrically connects] between a corresponding bridge first surface bond pad 156 and a corresponding bridge second surface bond pad 158 [the plurality of first pads],” [0017]). Deshpande teaches that “the increased high density microelectronic device-to-microelectronic device interconnect structures on the bridge may result in cost savings, modularity, and/or architectural flexibility,” (Deshpande, [0012]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Karhade with the teachings of Deshpande, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Deshpande, to reduce package size while also reducing costs and improving device performance.
Regarding claim 2, Karhade in view of Deshpande teaches: The bridge chip according to claim 1, wherein the bottom surface of the bridge chip is configured to electrically connect to the first metal wire layer (Karhade, FIG. 46 shows bottom surface of bridge component 110 [the bridge chip] electrically connected to conductive contacts 180 [the first metal wire layer], “the bridge component 110 [the bridge chip] may be conductively coupled to conductive contacts 180 [the first metal wire layer], [0072]).
Regarding claim 3, Karhade in view of Deshpande teaches: The bridge chip according to claim 1, wherein the bottom surface of the bridge chip is configured to be bonded to a first surface of the first metal wire layer by a plurality of bumps (Karhade, FIG. 46 shows bottom surface of bridge component 110 [the bridge chip] bonded to upper surface of conductive contacts 180 [the first surface of the first metal wire layer] by a plurality of low-temperature solder 166 [the plurality of bumps], [0075-0078]).
Regarding claim 4, Karhade in view of Deshpande teaches: The bridge chip according to claim 3, wherein the top surface (Karhade, FIG. 46, top surface of bridge component 110; Deshpande, FIG. 1, 2F, first surface 152 [the top surface of the bridge chip]) and the bottom surface of the bridge chip (Karhade, FIG. 46, bottom surface of bridge component 110; Deshpande, FIG. 1, 2F, second surface 154 [the bottom surface of the bridge chip]) each have an independent device structure (Karhade, FIG. 46, top surface of bridge component 110 shown having a different, i.e., independent, structure than bottom surface of bridge component 110; Deshpande, FIG. 1, 2F, first surface 152 [the top surface of the bridge chip] shown having a different, i.e., independent, structure than second surface 154 [the bottom surface of the bridge chip]), and the top surface and the bottom surface of the bridge chip are electrically connected through the lead (Deshpande, FIG. 1, 2F, “each of the plurality of through-bridge conductive vias 160 [the leads] extends [electrically connects] between a corresponding bridge first surface bond pad 156 [on the top surface] and a corresponding bridge second surface bond pad 158 [on the bottom surface],” [0017]), the first metal wire layer and the bump (Deshpande, FIG. 1, 2F, “The bridge second surface bond pads 158 [on the bottom surface] may be attached to corresponding substrate cavity bond pads 124 [analogous to the conductive contacts 180 of Karhade, i.e., the first metal wire layer] through a plurality of bridge-to-substrate interconnects 184, such as reflowable solder bumps or balls [analogous to the low-temperature solder 166 of Karhade, i.e., the bump],” [0017]).
Regarding claim 5, Karhade in view of Deshpande teaches: The bridge chip according to claim 1, wherein the plurality of first pads (Karhade, FIG. 46, conductive contacts 118, [0030]) are separately arranged on the top surface that is of the bridge chip and that is close to an outer edge (Karhade, FIG. 46 shows conductive contacts 118 [the plurality of first pads] separately arranged on the top surface of bridge component 110 [the bridge chip] and close to the left and right edges, i.e., close to an outer edge, [0030]).
Regarding claim 6, Karhade in view of Deshpande teaches: The bridge chip according to claim 1, wherein the top surface of the bridge chip (Karhade, FIG. 46, top surface of bridge component 110) further has other device structures that are not limited to the function of interconnecting the chips (Karhade, FIG. 57 shows dielectric material 112 and additional metal layers on top surface of bridge component 110, [0087]; Deshpande, FIG. 1 shows cavity bottom surface 118 on top surface of bridge 150, [0013]).
Regarding claim 7, Karhade in view of Deshpande teaches: A fan-out package structure comprising the bridge chip according to claim 1, comprising: a first metal wire layer (Karhade, FIG. 46, N-1 metal layer including conductive contacts 180, [0076]), a bridge chip molding layer located on a first surface of the first metal wire layer (Karhade, FIG. 57, dielectric material 112, [0087]), and a chip structure molding layer that is located on a surface of the bridge chip molding layer (Karhade, FIG. 57, surface insulation material 104, [0036]) and that is electrically connected to the surface of the bridge chip molding layer (Karhade, FIG. 57 shows surface insulation material 104 [the chip structure molding layer] electrically connected to the surface of dielectric material 112 [the bridge chip molding layer] by conductive contacts 114, [0029; 0036]; wherein the bridge chip molding layer comprises a bridge chip (Karhade, FIG. 57 shows dielectric material 112 [the bridge chip molding layer] comprises bridge component 110 [the bridge chip]), the first surface of the first metal wire layer is provided with a plurality of second pads (Karhade, FIG. 46 shows conductive contacts 180 [the second pads] on upper surface [the first surface] of N-1 metal layer [the first metal wire layer], “exposed pads of a metal layer,” [0076]; Deshpande, FIG. 1, cavity bond pads 124, 0017]) corresponding to first pads (Deshpande, FIG. 1 shows conductive contacts 124 [the second pads] aligned with, i.e., corresponding to, surface bond pads 156 [the first pads]), and the first pads and the corresponding second pads are connected through leads, so that a top surface of the bridge chip is electrically connected to the first metal wire layer (Karhade, [0072-0073]; Deshpande, FIG. 1, “each of the plurality of through-bridge conductive vias 160 [the leads] extends between [electrically connects] a corresponding bridge first surface bond pad 156 [the first pads, the top surface of the bridge chip] and a corresponding bridge second surface bond pad 158 [shown connected to cavity bond pads 124 [the first metal wire layer] by solder balls 184],” [0017]).
Regarding claim 8, Karhade in view of Deshpande teaches: The fan-out package structure according to claim 7, wherein a second metal wire layer is further provided between the bridge chip molding layer and the chip structure molding layer (Karhade, FIG. 57 shows conductive contacts 114 of N metal layer [the second metal wire layer] between dielectric material 112 [the bridge chip molding layer] and surface insulation material 104 [the chip structure molding layer]), the second metal wire layer is located on the surface of the bridge chip molding layer (Karhade, FIG. 57 shows N metal layer [the second metal wire layer] on the surface of dielectric material 112 [the bridge chip molding layer], [0029]) and electrically connected to a chip connecting structure of a bridge chip in the bridge chip molding layer (Karhade, FIG. 57 shows N metal layer [the second metal wire layer] electrically connected to bridge component 110 [the bridge chip in the bridge chip molding layer] by solder 106 [the chip connecting structure], [0032]), the chip structure molding layer is located on a surface of the second metal wire layer (Karhade, FIG. 57 shows surface insulation material 104 [the chip structure molding layer] located on upper surfaces of conductive contacts 114 [the second metal wire layer]), and at least two chips of the chip structure molding layer are electrically connected to the second metal wire layer (Karhade, FIG. 57 shows microelectronic components 130-1 and 130-2 [at least two chips] electrically connected to conductive contacts 114 [the second metal wire layer], [0029]).
Regarding claim 9, Karhade in view of Deshpande teaches: The fan-out package structure according to claim 7, wherein when a bottom surface of the bridge chip is bonded to a first surface of the first metal wire layer by a plurality of bumps (Karhade, FIG. 46 shows bottom surface of bridge component 110 [the bridge chip] bonded to upper surface of conductive contacts 180 [the first surface of the first metal wire layer] by a plurality of low-temperature solder 166 [the plurality of bumps], [0075-0078]), a curing adhesive is filled around the plurality of bumps between the bottom surface of the bridge chip and the first metal wire layer (Karhade, FIG. 46 shows polymer material 186 [the curing adhesive] filled around the low-temperature solder 166 [the plurality of bumps] between the bottom surface of bridge component 110 [the bridge chip] and conductive contacts 180 [the first metal wire layer], [0079]).
Regarding claim 10, Karhade in view of Deshpande teaches: The fan-out package structure according to claim 7, wherein the lead (Deshpande, FIG. 1, 2F, conductive via 160 [the lead], [0017]) is a copper wire or a gold wire. (Deshpande, conductive via 160 [the lead] comprises copper, [0022]; Karhade, copper or gold are known conductive materials [0076]).
Regarding claim 11, Karhade in view of Deshpande teaches: The fan-out package structure according to claim 7, wherein the plurality of second pads are separately arranged around the bridge chip (Karhade, FIG. 46 shows conductive contacts 180 [the second pads] separately arranged around lower surface of bridge component 110 [the bridge chip]; Deshpande, FIG. 1, cavity bond pads 124 [the second pads] shown separately arranged around lower surface of bridge 150 [the bridge chip], 0017]) and corresponding to the first pads (Deshpande, “bond pads formed in or on the bridge second surface to contact corresponding through-bridge conductive vias and attached to corresponding substrate cavity bond pads,” [0046).
Regarding claim 12, Karhade in view of Deshpande teaches: The fan-out package structure according to claim 8, wherein the bridge chip molding layer (Karhade, FIG. 57, dielectric material 112, [0087]) further comprises a conductive metal pillar (Karhade, FIG. 57, conductive material 108, [0108]) and a molding compound encapsulating the bridge chip, the conductive metal pillar and the lead (Karhade, FIG. 57 shows dielectric material 112 [the molding compound] encapsulating bridge component 110 [the bridge chip], conductive material 108 [the conductive metal pillar; Deshpande, FIG. 1 shows conductive via 160 [the lead] enclosed within bridge 150 [the bridge chip]), the first metal wire layer is electrically connected to the second metal wire layer through the conductive metal pillar (Karhade, “lines of conductive material 108 in one layer [the first metal wire layer] electrically coupled to lines of conductive material 108 in an adjacent layer [the second metal wire layer] by vias of the conductive material 108 [the conductive metal pillar],” [0028]; Deshpande, [0015]), and the chip connecting structure on the top surface of the bridge chip (Karhade, FIGs. 57, plurality of high-temperature solder 168, [0064]) is electrically connected to the second metal wire layer through a plurality of bumps (Karhade, FIGs. 57, solder 106 [the chip connecting structure] electrically connected to N metal layer [the second metal wire layer] through microbumps and conductive vias, [0063; 0087]).
Regarding claim 13, Karhade in view of Deshpande teaches: The fan-out package structure according to claim 8, wherein the chip structure molding layer (Karhade, FIGs. 2, 57, surface insulation material 104, [0036]) comprises a first chip and a second chip separately electrically connected to the second metal wire layer (Karhade, FIGs. 2, 57 show microelectronic components 130-1 and 130-2 [the first chip and the second chip] separately electrically connected to conductive contacts 114 [the second metal wire layer], [0029]) and a molding compound encapsulating the first chip and the second chip (Karhade, FIGs. 2, 57 show mold material 144 [the molding compound] encapsulating microelectronic components 130-1 and 130-2 [the first chip and the second chip], [0035]), and the bridge chip is electrically connected to the first chip and the second chip separately through the second metal wire layer (Karhade, FIGs. 2, 57, “microelectronic components 130 [the first chip and the second chip] may use the electrical pathways [electrical connections] through the bridge component 110 [the bridge chip] (and may use other circuitry within the bridge component 110, when present) to achieve a higher density interconnection between them, relative to interconnections made via the conductive contacts 114 [the second metal wire layer],” [0033]; Deshpande, FIGs. 1, 2E, [0016; 0024]).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Karhade in view of Deshpande and further in view of Sikka et al., US 2021/0159141 A1 (hereinafter Sikka).
Regarding claim 14, Karhade in view of Deshpande teaches: The fan-out package structure according to claim 7, further comprising a substrate (Karhade, FIG. 57, substrate 102) (Karhade, FIG. 57 shows substrate 102 [the substrate] electrically connected to lower surface of conductive contacts 180 [the second surface of the first metal wire layer]).
Karhade in view of Deshpande is silent regarding: a heat dissipating lid.
However, Sikka, in disclosing a semiconductor package designed to transfer heat away from one or more bridges within the package, teaches: a heat dissipating lid (Sikka, FIG. 2, lid 130, “lid 130 to dissipate [heat] away from the package,” [0036]). Sikka teaches that the lid improves package structural integrity, reduces warpage, and improves cooling, (Sikka, [0035-0038]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Karhade in view of Deshpande with the teachings of Sikka, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Sikka, to conduct heat away from the bridge chip, thereby improving device performance and reliability.
Regarding claim 15, Karhade in view of Deshpande and further in view of Sikka teaches: The fan-out package structure according to claim 14, wherein the second surface of the first metal wire layer has a solder ball (Karhade, FIG. 57, solder 166 [the solder ball], [0064]), a part of the solder ball located at a corresponding position of the bridge chip is electrically connected to the second pad (Karhade, FIG. 57, solder 166 [the solder ball] at N-1 metal layer in contact with, i.e., electrically connected to, conductive contacts 180 [the second pad], [0072]), and the top surface of the bridge chip is electrically connected to the substrate through the lead, the second pad, and the part of the solder ball located at a corresponding position of the bridge chip (Karhade, [0072-0073]; Deshpande, FIG. 1, “each of the plurality of through-bridge conductive vias 160 [the leads] extends between [electrically connects] a corresponding bridge first surface bond pad 156 [the first pads, the top surface of the bridge chip] and a corresponding bridge second surface bond pad 158 [shown connected to cavity bond pads 124 [the second pad] by solder balls 184],” [0017]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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