DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed August 10, 2026. Claims 1, 9, 15, 18, and 19 have been amended. No claims have been added. Claim 17 has been canceled. Claims 15-16, and 18-20 stand withdrawn. Currently, claims 1-14 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Benetik et al. (US 20050208728 A1) herein after “Benetik” in view of Sowlati et al. (US 6570210 B1) herein after “Sowlati”.
Regarding claim 1, Figs. 5 and 7 of Benetik disclose a structure (Fig. 5, capacitance structure K, ¶ [0039]) comprising:
a first conductive line (Fig. 5, metallization plane 3, ¶ [0047]) within a dielectric material (Fig. 5, “This insulating layer has a capacitance structure K integrated in it”, ¶ [0039]), the dielectric material (“insulating layer”) extending over the first conductive line (3);
a second conductive line (Fig. 5, metallization planes 4, ¶ [0047]) within the dielectric material (“insulating layer”) and substantially vertically aligned with the first conductive line (3); and
a conductive pillar (Fig. 5, bars 41a to 46a, ¶ [0047]) within the dielectric material (“insulating layer”) between the first conductive line (3) and the second conductive line (4), wherein the conductive pillar (41a-46a) includes one of an upper surface contacting a lower surface of the second conductive line (4) and a lower surface contacting an upper surface of the first conductive line (3), wherein a vertical thickness of the conductive pillar (41a-46a) is less than a vertical thickness between the first conductive line (3) and the second conductive line (4), a first capacitive junction (Fig. 7, second capacitance components C2, ¶ [0044]) is between the conductive pillar (41a-46a) and one of the first conductive line (3) and the second conductive line (4).
Benetik discloses each of the first plurality of conductive lines (3) having an different potentials (“vertically and laterally adjacent lines being at different potentials”, ¶ [0004]) relative to an adjacent conductive line of the first plurality of conductive lines (3), but fails to explicitly disclose wherein the first conductive line has an opposite polarity relative to a first horizontally adjacent conductive line within the dielectric material;
wherein the second conductive line has an opposite polarity relative to a second horizontally adjacent conductive line within the dielectric material; and
the conductive pillar having a first polarity, wherein the first conductive line has a second polarity opposite the first polarity.
In the similar field of endeavor of capacitor structures, Fig. 2 of Sowlati discloses wherein the first conductive line (Fig. 2, electrode “A” in fifth conductor level L5) has an opposite polarity relative to a first horizontally adjacent conductive line (Fig. 2, electrode “B” in fifth conductor level L5) within the dielectric material (Fig. 2, second and fifth dielectric layers 29, 32, col. 3, line 55) (“all the "A" plates are of a first polarity and all the "B" plates are of a second polarity, opposite to the first polarity”, col. 1, lines 45-48);
wherein the second conductive line (Fig. 2, electrode “B” in first conductor level L1) has an opposite polarity relative to a second horizontally adjacent conductive line (Fig. 2, electrode “A” in first conductor level L1) within the dielectric material (29, 32); and
the conductive pillar (Fig. 2, vertical pillars 22, col. 3, lines 2-3) having a first polarity (“The pillars 22 denoted by the letter "B" are electrically connected to the top and bottom "B" lines 23,24”, col. 3, lines 50-53), wherein the first conductive line (electrode “A” in first conductor level L1) has a second polarity opposite the first polarity (“all the "A" plates are of a first polarity and all the "B" plates are of a second polarity, opposite to the first polarity”, col. 1, lines 45-48).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive lines layer of Benetik to include the alternating polarity as disclosed by Sowlati, to obtain the desired capacitance density (see Sowlati, col. 4, lines 5-8).
Regarding claim 2, Benetik and Sowlati together disclose the structure of claim 1 as applied above, and Benetik further discloses wherein the first conductive line (3) and the second conductive line (4) are each one of a plurality of conductive lines extending horizontally outward from a conductive wire (“The lines 31, 33, 35, 42, 44 and 46 are electrically connected to a first connecting line (not shown)”, ¶ [0047]).
Regarding claim 3, Benetik and Sowlati together disclose the structure of claim 1 as applied above, and Fig. 5 of Benetik further discloses wherein the conductive pillar (41a-46a) is one of a plurality of pillars within the dielectric material (“insulating layer”), each of the plurality of pillars having a horizontal length less than a horizontal length of the first conductive line (3) or the second conductive line (4).
Regarding claim 8, Benetik and Sowlati together disclose the structure of claim 1 as applied above, and Fig. 7 of Benetik further discloses wherein a second capacitive junction (Fig. 7, first capacitance component C1, ¶ [0044]) is between the conductive pillar (41a-46a) and a horizontally adjacent conductive pillar (41a-46a).
Regarding claim 9, Figs. 5 and 7 of Benetik discloses a structure (K) comprising:
a first plurality of conductive lines (3) within a dielectric material (“insulating layer”);
a second plurality of conductive lines (4) on the dielectric material (“insulating layer”) and substantially vertically aligned with the first plurality of conductive lines (3), each of the second plurality of conductive lines (4) having an alternating polarity relative to an adjacent conductive line in the second plurality of conductive lines (4); and
a plurality of conductive pillars (41a-46a) within the dielectric material (“insulating layer”), wherein each of the plurality of conductive pillars (41a-46a) includes one of an upper surface interfacing with a lower surface of the second plurality of conductive lines (4) and a lower surface interfacing with an upper surface of the first plurality of conductive lines (3) conductive line, a vertical thickness of each conductive pillar is less than a vertical thickness between the plurality of first conductive lines (3) and the plurality of second conductive, a first capacitive junction (C2) is between each conductive pillar and one of the first plurality of conductive lines (3) and the second plurality of conductive lines (4), and a second capacitive junction (C3) is between two horizontally adjacent conductive pillars of the plurality of conductive pillars (41a-46a).
Benetik discloses each of the first plurality of conductive lines (3) having an different potentials (“vertically and laterally adjacent lines being at different potentials”, ¶ [0004]) relative to an adjacent conductive line of the first plurality of conductive lines (3), but fails to explicitly disclose each of the first plurality of conductive lines having an alternating polarity relative to an adjacent conductive line of the first plurality of conductive lines;
the second plurality of conductive lines having an alternating polarity relative to an adjacent conductive line in the second plurality of conductive lines;
the plurality of conductive pillars having a first polarity,
the first plurality of conductive lines having a second polarity opposite the first polarity.
In the similar field of endeavor of capacitor structures, Fig. 2 of Sowlati discloses each of the first plurality of conductive lines (electrode “A” in fifth conductor level L5) having an alternating polarity relative to an adjacent conductive line (electrode “B” in fifth conductor level L5) of the first plurality of conductive lines (“all the "A" plates are of a first polarity and all the "B" plates are of a second polarity, opposite to the first polarity”, col. 1, lines 45-48);
the second plurality of conductive lines (electrode “B” in fifth conductor level L5) having an alternating polarity relative to an adjacent conductive line (electrode “A” in fifth conductor level L5) in the second plurality of conductive lines (“all the "A" plates are of a first polarity and all the "B" plates are of a second polarity, opposite to the first polarity”, col. 1, lines 45-48);
the plurality of conductive pillars (22) having a first polarity (“The pillars 22 denoted by the letter "B" are electrically connected to the top and bottom "B" lines 23,24”, col. 3, lines 50-53),
the first plurality of conductive lines (electrode “A” in fifth conductor level L5) having a second polarity opposite the first polarity (“all the "A" plates are of a first polarity and all the "B" plates are of a second polarity, opposite to the first polarity”, col. 1, lines 45-48).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive lines layer of Benetik to include the alternating polarity as disclosed by Sowlati, to obtain the desired capacitance density (see Sowlati, col. 4, lines 5-8).
Regarding claim 10, Benetik and Sowlati together disclose the structure of claim 9 as applied above, and Fig. 5 of Benetik further discloses comprising:
a first conductive wire (“The lines 31, 33, 35, 42, 44 and 46 are electrically connected to a first connecting line (not shown)”, ¶ [0047]) coupled to the first plurality of conductive lines (3), wherein each of the first plurality of conductive lines (3) extends horizontally outwardly from the first conductive wire; and
a second conductive wire (“The lines 32, 34, 36, 41, 43 and 45 are electrically connected to a second connecting line (not shown)”, ¶ [0047]) coupled to the second plurality of conductive lines (4), wherein each of the second plurality of conductive lines (4) extends horizontally outwardly from the second conductive wire.
Claims 4-6, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Benetik (US 20050208728 A1) and Sowlati (US 6570210 B1) in further view of Chen et al. (US 20100123213 A1) herein after “Chen”.
Regarding claim 4, Benetik and Sowlati together disclose the structure of claim 1 as applied above, but the combination fails to explicitly disclose wherein the dielectric material includes an etch stop layer (ESL) vertically between the conductive pillar and one of the first conductive line and the second conductive line.
In the similar field of endeavor of MIM capacitors, Fig. 4 of Chen discloses wherein the dielectric material (Fig. 4, “A number of caps and etch-stops, referred to collectively as caps 46”, ¶ [0039]) includes an etch stop layer (ESL) (Fig. 4, “Caps 46 may also include etch-stops for use during processing”, ¶ [0039]) vertically between the conductive pillar (Fig. 4, metal layer M3, ¶ [0030]) and one of the first conductive line (Fig. 4, metal layer M2, ¶ [0030]) and the second conductive line.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric material layer of Benetik to include the etch stop layer as disclosed by Chen, to prevent diffusion of conductive material (see Chen, ¶ [0039]).
Regarding claim 5, Benetik, Sowlati and Chen together disclose the structure of claim 4 as applied above, but Benetik and Sowlati fail to disclose wherein the ESL vertically interfaces with the conductive pillar and each of a plurality of additional conductive pillars between the first conductive line and the second conductive line.
In the similar field of endeavor of MIM capacitors, Fig. 4 of Chen discloses wherein the ESL (46) vertically interfaces with the conductive pillar (M3) and each of a plurality of additional conductive pillars between the first conductive line (M2) and the second conductive line.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric material layer of Benetik to include the etch stop layer as disclosed by Chen, to prevent diffusion of conductive material (see Chen, ¶ [0039]).
Regarding claim 6, Benetik, Sowlati and Chen together disclose the structure of claim 4 as applied above, but Benetik and Sowlati fail to disclose wherein the dielectric material further includes an inter-level dielectric (ILD) layer on the ESL, the ILD layer having a different composition from the ESL.
In the similar field of endeavor of MIM capacitors, Fig. 4 of Chen discloses wherein the dielectric material further includes an inter-level dielectric (ILD) layer (Fig. 4, dielectric material 52, ¶ [0039]) on the ESL (46), the ILD layer (52) having a different composition from the ESL (46) (“dielectric material 52 may have a dielectric constant .epsilon. of 2.5 .epsilon..sub.0, whereas caps 46 may have dielectric constants ranging from 2.7 .epsilon..sub.0 to 4.5 .epsilon..sub.0”, ¶ [0041]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric material layer of Benetik to include the materials as disclosed by Chen, to obtain the desired capacitive coupling (see Chen, ¶ [0041]).
Regarding claim 11, Benetik and Sowlati together disclose the structure of claim 9 as applied above, and Benetik further discloses the dielectric material between each of the plurality of conductive pillars and the respective first conductive line or the respective second conductive line (Fig. 5, “This insulating layer has a capacitance structure K integrated in it”, ¶ [0039]), but Benetik and Sowlati fail to disclose wherein the dielectric material includes an etch stop layer (ESL).
In the similar field of endeavor of MIM capacitors, Fig. 4 of Chen discloses wherein the dielectric material (Fig. 4, “A number of caps and etch-stops, referred to collectively as caps 46”, ¶ [0039]) includes an etch stop layer (ESL) (Fig. 4, “Caps 46 may also include etch-stops for use during processing”, ¶ [0039]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric material layer of Benetik to include the etch stop layer as disclosed by Chen, to prevent diffusion of conductive material (see Chen, ¶ [0039]).
Regarding claim 12, Benetik, Sowlati and Chen together disclose the structure of claim 11 as applied above, but Benetik and Sowlati fail to disclose wherein the dielectric material further includes an inter-level dielectric (ILD) layer on the ESL, the ILD layer having a different composition from the ESL.
In the similar field of endeavor of MIM capacitors, Fig. 4 of Chen discloses wherein the dielectric material (52) further includes an inter-level dielectric (ILD) layer (52) on the ESL (46), the ILD layer (52) having a different composition from the ESL (46) (“dielectric material 52 may have a dielectric constant .epsilon. of 2.5 .epsilon..sub.0, whereas caps 46 may have dielectric constants ranging from 2.7 .epsilon..sub.0 to 4.5 .epsilon..sub.0”, ¶ [0041]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric material layer of Benetik to include the materials as disclosed by Chen, to obtain the desired capacitive coupling (see Chen, ¶ [0041]).
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Benetik (US 20050208728 A1), Sowlati (US 6570210 B1) and Chen (US 20100123213 A1) in further view of Tien et al. (US 20200343137 A1) herein after “Tien”.
Regarding claim 7, Benetik, Sowlati and Chen together disclose the structure of claim 6 as applied above, but the combination fails to disclose wherein the ILD layer includes silicon carbonitride (SiCN).
In the similar field of endeavor of integrated circuits, Fig. 2 of Tien discloses wherein the ILD layer (Fig. 2, first dielectric layer 104, ¶ [0022]) includes silicon carbonitride (SiCN) (“the material of the first dielectric layer 104 includes silicon carbide (SiC), silicon dioxide (SiO.sub.2), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon carbon nitride (SiCN)”, ¶ [0022]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric material layer of Benetik to include the materials as disclosed by Tien, to obtain the desired insulating properties (see Tien, ¶ [0022]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 13, Benetik, Sowlati and Chen together disclose the structure of claim 12 as applied above, but the combination fails to disclose wherein the ILD layer includes silicon carbonitride (SiCN).
In the similar field of endeavor of integrated circuits, Fig. 2 of Tien discloses wherein the ILD layer (104) includes silicon carbonitride (SiCN) (“the material of the first dielectric layer 104 includes silicon carbide (SiC), silicon dioxide (SiO.sub.2), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon carbon nitride (SiCN)”, ¶ [0022]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric material layer of Benetik to include the materials as disclosed by Tien, to obtain the desired insulating properties (see Tien, ¶ [0022]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Benetik (US 20050208728 A1) and Sowlati (US 6570210 B1) in further view of Tien (US 20200343137 A1).
Regarding claim 14, Benetik and Sowlati together disclose the structure of claim 9 as applied above, but the combination fails to disclose wherein a material composition of the plurality of conductive pillars is different from a material composition of the first plurality of conductive lines or the second plurality of conductive lines.
In the similar field of endeavor of integrated circuits, Fig. 2 of Tien discloses wherein a material composition of the plurality of conductive pillars (Fig. 2, metal lines 105, ¶ [0022]) is different from a material composition of the first plurality of conductive lines (Fig. 2, contacts 102C, ¶ [0018]) or the second plurality of conductive lines (“The conductive material includes a metal, such as cobalt, tungsten, copper, aluminum, gold, silver”, “the material of the metal lines 105 includes Ta, TaN, TiN”, ¶ [0021] and [0023]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Benetik with the conductive materials as disclosed by Tien, to improve production quality (see Tien, ¶ [0012]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 11:30am-7pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
