Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-6 and 15-20 in the reply filed on 7/2/2026 is acknowledged. The traversal is on the ground(s) that no unreasonable search and examination burden exists because a search of the claims of Group II would be similarly applicable to the claims of Group II. This is not found persuasive because the claims of Group II require the search of deposition processes for different materials, such as the top spacer cover, top and bottom epitaxial sources/drains, and dummy contacts, and anneal processes. These processes are not search requirements for claims in Group I.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "428" and "212" have both been used to designate “bottom S/D contact” in FIG. 4N-4O. The specification indicates that FIG. 4N shows “bottom S/D contact 212” but the figure uses “428”, which corresponds to the “dummy contact”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites, “the top interface and the bottom interface each comprise metal silicide”. While the specification shows that the claimed intermediate structure has a top interface comprising metal silicide, there is no indication that there is a metal silicide interface between the bottom dummy contact and the bottom epi S/D. Para. 0062 and FIG. 4N show that “bottom interface 216” is formed after “bottom S/D contact 212” is formed. The claim recites a feature pertinent to another stage in the manufacturing of the device.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. US 20240072136 A1 (hereinafter referred to as Lin).
Regarding claim 1, Lin teaches
A semiconductor structure forming a complementary field-effect transistor (“CFET 5000” para. 0072 FIG. 1ZG-1, 1ZG-2, 1ZG-3, 5), comprising:
a metal gate (“gate structure 1506-2” para. 0066);
a bottom field effect transistor module (TRB) (structure including “semiconductor layers 108A” and “source/drain features 1102P” para. 0026, 0039), the bottom FET module comprising:
a plurality of channel layers (“semiconductor layers 108A”) extending through the metal gate in a first direction; and
a bottom source/drain (S/D) contact (“source/drain contacts 2702” para. 0068) electrically connected to the plurality of channel layers via a bottom epitaxial (epi) S/D (“source/drain features 1102P” are grown through epitaxy processes, para. 0040) and a bottom interface (“silicide features 2706” para. 0069); and
a top FET module (structure including “semiconductor layers 108C” and “source/drain features 1302N”, para. 0026,0043) stacked on the bottom FET module in a second direction that is orthogonal to the first direction (the second transistor structure is above the first as seen in FIG. 1ZG-1, 1ZG-2), the top FET module comprising:
a plurality of channel layers (“semiconductor layers 108C”) extending through the metal gate in the first direction; and
a top source/drain (S/D) contact (“source/drain contacts 2402” para. 0064) electrically connected to the plurality of channel layers via a top epitaxial (epi) S/D (“source/drain features 1302N” are grown through epitaxy processes, para. 0044) and a top interface (“silicide features 2408”), wherein the bottom S/D contact and the top S/D contact each comprise cobalt (Co) or tungsten (W) (“source/drain contacts 2402” and “source/drain contacts 2402” comprise W or Co, para. 0064,0068).
Regarding claim 2, Lin teaches the semiconductor structure of claim 1, wherein the metal gate comprises cobalt (Co) or tungsten (W) (“gate electrodes 1504A” and “gate electrodes 1504B” of “gate structure 1506-2” comprise W or Co, para. 0053-0054).
Regarding claim 3, Lin teaches the semiconductor structure of claim 1, wherein the plurality of channel layers in the top FET module and the plurality of channel layers in the bottom FET module each comprise silicon (“semiconductor layers 108 are formed of silicon” para. 0024).
Regarding claim 4, Lin teaches the semiconductor structure of claim 1, wherein the bottom epi S/D is p-type doped (“source/drain features 1102P” are p-type, para. 0040) and the top epi S/D is n-type doped (“source/drain features 1302N” are n-type, para. 0044).
Regarding claim 6, Lin teaches the semiconductor structure of claim 1, wherein the top interface and the bottom interface each comprise metal silicide (“silicide features 2408” and “silicide features 2706” are silicides, as indicated in their names, para. 0065,0069).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1 above, in view of Mertens et al. US 20230420544 A1 (hereinafter referred to as Mertens), and in view of Xie et al. US 20210265348 A1 (hereinafter referred to as Xie).
Lin teaches semiconductor structure of claim 1 but fails to teach wherein the bottom epi S/D is n-type doped and the top epi S/D is p-type doped.
Nevertheless, Mertens teaches that the lower “source/drain bodies 150” may be doped either with n-type or p-type dopants as desired (para. 0076) while “source/drain bodies 160” may be n-type or p-type (para. 0089). Similarly, “source and drain regions 302” is Xie may comprise either n-type dopant or p-type dopant and “source drain regions 502” is oppositely doped (para. 0061). While “source/drain features 1102P” are n-type regions, the examiner understands this is a matter of design choice as long as “source/drain features 1302N” are oppositely doped. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the choice of dopant for “source/drain features 1102P” is merely subject to design preference and is one of two obvious choices for forming a CFET device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure in Lin with the doping of epi S/D regions as taught in Mertens and Xie. The dopant for the bottom epi S/D is a design choice between n-type and p-type, where either choice enables the formation of a CFET device.
Allowable Subject Matter
Claims 15-19 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 15 recites “a metal gate”, “a dummy contact” in a “bottom field effect transistor module”, and “a top source/drain contact”. Liao et al. US 20210366907 A1 teaches in FIG. 16A a “first source feature 228S” on a “substrate 202” and “source contact 250” in contact with “second source feature 244S” above. However, a first gate structure is formed in the bottom transistor structure and a separate second gate structure is formed in the top structure (see FIG. 17A-17B para. 0044). Although Lin teaches a common metal gate for bottom and top transistors, it is not obvious to modify the bottom contact in Lin with the dummy contact in Liao because of their processes for forming and their structure. It is algo not obvious to modify the metal gates in Liao with the common metal gate in Lin because this substantially modifies the function of the device and would require non-obvious structural modification to achieve. Therefore, claim 15 is considered allowable.
Claims 16-19 are allowed based on their dependency on claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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