DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As of March 17, 2026, no information disclosure statement has been made of record. Examiner reminds Applicant of their duty of disclosure under 37 CFR 1.56.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2001/0051436 A1) (“Kim”), in view of Hayashi (JP H09-181363 A) by means of machine translation (“Hayashi”), in view of Dimmler et al. (US 2004/0041186 A1) (“Dimmler”).
Regarding claim 1, Kim teaches at least in figure 1:
a source region and a drain region (104s) disposed in a substrate (102);
a channel region (106) disposed in the substrate (102) between the source region and the drain region (104s); and
a gate structure disposed on the channel region, wherein the gate structure comprises (gate structure is defined below and it is on 106):
a first oxide layer (110/108) comprises a metal oxide (figure 1 shows Mg),
wherein the metal oxide (110/108) comprises at least one selected from magnesium oxide, aluminum oxide and tantalum oxide (figure 1 shows MgO);
a first ferroelectric layer (110), comprising a ferroelectric material (figure 1 labels this ferroelectric film); and
a gate metal layer (118), stacked, in order, on the channel region (106),
wherein the ferroelectric material (112) is disposed on the metal oxide layer (110/108).
Kim is silent with respect to:
Wherein the first oxide layer is a first crystal oxide layer, comprising a metal oxide having a crystalline structure comprises magnesium oxide having a crystal lattice orientation (001) or (110).
Based upon claim 2, Examiner understands this limitation to encompass polycrystalline magnesium oxide.
Hayashi teaches:
polycrystalline magnesium oxide having orientations of (001) and (111) can be used in ferroelectric devices. Pg. 3 last ¶.
It would have been obvious to one of ordinary skill in the art to include the polycrystalline MgO of Hayashi into the device of Kim as Hayashi teaches that this material is less expensive than single crystal MgO, and easier to produce in mass production than single crystal MgO. ¶ 0003. Hayashi teaches that by forming a polycrystalline MgO film one can form the MgO film have the same workability and performance of single crystal MgO film at less cost and easier to mass manufacture. ¶ 0006. Thus, it would have been obvious to one of ordinary skill it the art to incorporate the teachings of Hayashi into Kim.
Kim and Hayashi do not teach:
Wherein the metal oxide of the first crystal oxide layer is disposed directly on the channel region.
Dimmler teaches at least in figure 3:
Wherein the metal oxide of the first crystal oxide layer (104; ¶ 0030, where 104 can be SiO2, SiN, or MgO) is disposed directly on the channel region (103).
It would have been obvious to one of ordinary skill in the art to replace the gate dielectric of Kim with the gate dielectric of Dimmler as it would produce an equivalent device, ferroelectric transistor, with less process steps as one would not need to form the additional silicon dioxide gate insulator. This would in turn lead to a simpler product which can be produced faster and cheaper.
Regarding claim 2,
wherein the first crystal oxide layer comprises magnesium oxide having a crystal lattice orientation (001), (110) or (111) (see claim 1).
Regarding claim 5, the prior art teaches:
wherein the first crystal oxide layer (Kim 110/108; Dimmler 104 ) has at least 80% by weight of the metal oxide having the crystalline structure (it would have been obvious based upon the process described by Yoon, that one would want the first crystal oxide layer to be at least 80% by weight to be a crystalline structure this is because Yoon discusses the entire layer as being a single crystalline layer. Yoon pg. 2661 at col. 1.
Regarding claim 6, Kim teaches at least in figure 1:
wherein the first crystal oxide layer (110/108) further extends directly (the combination of Kim and Dimmler teach this) a portion of the source region and a portion of the drain region (104s; where 110/108 covers a portion of 104s).
Regarding claim 7, Kim teaches at least in figure 1:
wherein the gate metal layer (118) directly contacts the first ferroelectric layer (112).
Claim(s) 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Hayashi, in view of Dimmler, in view of Maeda (US 2002/0025637 A1) (“Maeda”).
Regarding claim 21,
Claim 1 teach all of the limitations of claim 21 with the exception of…
The crystal oxide layer is tantalum oxide.
Dimmler teaches:
The oxide layer can be selected from MgO or aluminum oxide. ¶ 0030.
Based upon the teachings contained in claim 1 it would have been obvious that one would want the oxide layer to be crystalline and it could be made of MgO or aluminum oxide.
Maeda teaches:
That MgO, Al2O3 (aluminum oxide), and Ta2O5 (tantalum oxide) are all obvious variants of each other and can be used the transistor of Kim. ¶ 00053.
Therefore, under MPEP 2144.06 and 07, it would have been obvious to one of ordinary skill in the art to substitute one art preconized equivalent for another as they are all suitable for the intended purpose.
Regarding claim 22,
Claim 22 contains limitations found in claim 1, and is rejected for the reasons contained in claim 1.
Regarding claim 23,
Claim 23 is rejected for the same reasons as claim 6 above.
Regarding claim 24,
Claim 24 is rejected for the same reasons as claim 6 above.
Claim(s) 3-4, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Yoon, in view of Dimmler, in view of Maeda, in view of Lee (US 2015/0287802 A1) (“Lee”).
Regarding claim 3, Kim teaches:
The ferroelectric material is PZT.
Lee teaches:
Hafnium oxide (HfO2) is an art recognized equivalent ferroelectric material to PZT. ¶ 0017. MPEP 2144.06, and is suitable to be used in a transistor. MPEP 2144.07
Regarding claim 4, Lee teaches:
spacers (40) disposed at opposite sides of the gate structure (36).
It would have been obvious to one of ordinary skill in the art to add spacers to the gate of Kim in order to provide electrical insulation to the gate from the source and drain electrodes.
The combination of references teaches:
wherein the first crystal oxide layer (Kim 110) extends directly on inner sidewalls of the spacers (Lee 40).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Yoon, in view of Dimmler, in view of Maeda, in view of Liu (US 2018/0061959 A1) (“Liu”).
Regarding claim 8, Kim does not teach:
wherein a top surface of the first crystal oxide layer, a top surface of the first ferroelectric layer and a top surface of the gate metal layer are flush with each other.
This is because Kim teaches a planar gate.
Liu teaches:
That a replacement gate is an alternative (i.e. an art recognized equivalent) to a planar gate. ¶ 0016)
Based upon figure 1 of Liu:
It would have been obvious that the top surface of first crystal oxide layer (Kim 110/108), a top surface of the first ferroelectric layer (Kim 112) and a top surface of the gate metal layer (Kim 118) are flush with each other (as shown in Liu figure 1). This is because how the structure of a replacement gate is a variation of the planar gate.
Regarding claim 11,
Claim 11 is taught by claims 1 and 8 above with the exception of:
a work function layer disposed on the first crystalline oxide layer; and a gate electrode layer disposed on the work function layer
However, Liu teaches that the metal gate 38 can be a multi-layered structure which include a work function layer. ¶ 0015.
Claim(s) 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Yoon, in view of Dimmler, in view of Maeda, in view of Tsai et al. (US 2019/0067488 A1) (“Tsai”).
Regarding claim 25, The previous prior art does not teach:
Wherein crystal oxide layer has a u-shape in cross-section.
This is because the prior art teaches a standard planar transistor.
Tsai teaches at least in figure 1A:
Wherein crystal oxide layer (103, where 103 is equivalent to the previous prior art’s crystal oxide layer) has a u-shape in cross-section (figure 1A).
It would have been obvious to one of ordinary skill in the art to change the shape of the crystal oxide layer as the device of Tsai uses a replacement gate process. The replacement gate process is an alternative process to form the gate insulator (crystal oxide layer) and gate of the prior art.
Regarding claim 26, Tsai teaches at least in figure 1A:
Wherein the ferroelectric layer (105) has a u-shape in cross-section (figure 1A).
Claim(s) 27-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Yoon, in view of Dimmler, in view of Maeda, in view of Lee, in view of Tsai.
Regarding claim 27,
Claim 27 is rejected for the same reasons as claim 4 above.
Regarding claim 28,
Claim 1 teaches all of the limitations of claim 28 with the exception of a work function layer.
Claim 28s high-k layer is the same a claims 1 and 3’s ferroelectric layer. Where the ferroelectric layer can be PZT or HfO2.
Tsai teaches at least in figure 1A:
That one can include a work function layer between the gate electrode 106 and the ferroelectric layer 105. ¶¶ 0045-47.
Based upon the above, claim 28 is obvious in light of the prior art.
Regarding claim 29,
Claim 29 contains subject matter found in claim 1, and is rejected for the same reasons as claim 1 above.
Regarding claim 30,
Claim 30 contains subject matter found in claim 1, and is rejected for the same reasons as claim 1 above.
Regarding claim 31,
wherein the crystalline oxide layer is separated from the doped regions (the crystalline oxide layers of claim 28/1 are separated from the doped region (source/drain) of claim 28/1 as they are in their own discrete layers, and thus are separate structural elements.
Regarding claim 32,
Based upon the material disclosed by Applicant and based upon the material taught in claims 3-4 and 28 it would have been obvious that the material of the prior art would have the claimed dielectric constant as the Applicant’s material is the same as the prior art.
Response to Arguments
Applicant’s amendments, filed March 5, 2026, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the additional references cited above.
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898