Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on March 5th, 2024, and April 7th, 2025, filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of invention I in the reply filed on July 24th, 2026, is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 24th, 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "a semiconductor substrate" in line 2. It is unclear if the semiconductor substrate is the semiconductor substrate defined in Claim 1 or a second, different semiconductor substrate. For the purpose of examination, the limitation will be interpreted as “another semiconductor substrate”.
Claim 17 recites the limitation “the first portion” and “the second portion” in Lines 1-3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitations will be interpreted as “a first portion” and “a second portion”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 8-9, 11, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou et al. (2014/0217604 A1; hereinafter Chou).
Regarding Claim 1, Chou (figs. 7-8) teaches a semiconductor structure ([0014], 10, see fig. 1), comprising:
a first semiconductor die ([0014], 100, 200) comprising a semiconductor substrate (100) and
an interconnect structure (200) underlying the semiconductor substrate (100);
a second semiconductor die ([0014], 300) underlying and bonded to the first semiconductor die (100, 200), wherein
a maximum lateral dimension of the semiconductor substrate (100) of the first semiconductor die (100, 200) is less than that of the second semiconductor die (300); and
an insulating encapsulant ([0018], 140) disposed over the second semiconductor die (300) and at least laterally surrounding the semiconductor substrate (100) of the first semiconductor die (100, 200).
Regarding Claim 2, Chou (figs. 7-8) teaches the semiconductor structure of claim 1, wherein the first semiconductor die (100, 200) comprises a sidewall of the interconnect structure (sidewall of 200) and a sidewall of the semiconductor substrate (sidewall of 100) which is laterally displaced from the sidewall of the interconnect structure (sidewall of 200).
Regarding Claim 3, Chou (figs. 7-8) teaches the semiconductor structure of claim 2, wherein the insulating encapsulant (140) extends along the sidewall of the semiconductor substrate (sidewall of 100) and lands on an upper surface of the interconnect structure (top surface of 200) connected to the sidewall of the interconnect structure (sidewall of 200).
Regarding Claim 5, Chou (figs. 7-8) teaches the semiconductor structure of claim 1, wherein the first semiconductor die (100, 200) further comprises: a bonding structure ([0035]-[0036], 234, 236, see fig. 7) underlying the interconnect structure (200) and bonded to the second semiconductor die (300), wherein the insulating encapsulant (140) is vertically spaced apart from the second semiconductor die (300) by the interconnect structure (200) and the bonding structure (234, 236).
Regarding Claim 8, Chou (figs. 7-8) teaches the semiconductor structure of claim 1, wherein the insulating encapsulant (140) comprises: a first portion (left portion of 140) extending along a first sidewall of the first semiconductor die (left sidewall of 100); and a second portion (right portion of 140) extending along a second sidewall of the first semiconductor die (right sidewall of 100) which is laterally displaced from the first sidewall of the first semiconductor die (left sidewall of 100).
Regarding Claim 9, Chou (figs. 7-8) teaches the semiconductor structure of claim 8, wherein outer sidewalls of the first and second portions of the insulating encapsulant (outer sidewalls of 140) are substantially aligned with at least a portion of an outer sidewall of the interconnect structure (outer sidewalls of 200) of the first semiconductor die (100, 200).
Regarding Claim 11, Chou (figs. 7-8) teaches the semiconductor structure of claim 1, wherein a bonding interface ([0035]-[0037], where 236 and 312 meet, see fig. 7) of the first (100, 200) and second semiconductor dies (200) is free of solder material ([0026], conductive bumps may be direct metal-to-metal bonding).
Regarding Claim 21, Chou (figs. 7-8) teaches a semiconductor structure ([0014], 10, see fig. 1), comprising:
a first semiconductor die ([0014], 100, 200) comprising a semiconductor substrate (100),
an interconnect structure (200) underlying the semiconductor substrate (100), and
a first bonding structure ([0035]-[0036], 234, 236, see fig. 7) underlying the interconnect structure (200);
a second semiconductor die ([0014], 300) underlying the first semiconductor die (100, 200), wherein the first bonding structure (234, 236) of the first semiconductor die (100, 200) is bonded to the second semiconductor die (300); and
an insulating encapsulant ([0018], 140) disposed over the second semiconductor die (300) and at least laterally surrounding the semiconductor substrate (100) of the first semiconductor die (100, 200), the insulating encapsulant (140) being vertically spaced apart from the second semiconductor die (300) by the interconnect structure (200) and the first bonding structure (234, 236).
Regarding Claim 22, Chou (figs. 7-8) teaches the semiconductor structure of claim 21, wherein the insulating encapsulant (140) extends along the semiconductor substrate (100) and lands on an upper surface of the interconnect structure (top surface of 200).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to Claim 2 above, and further in view of Yu et al. (2021/0118759 A1; hereinafter Yu).
Regarding Claim 4, Chou (figs. 7-8) teaches the semiconductor structure of claim 2, wherein an upper surface of the interconnect structure (top surface of 200) connected to the sidewall of the interconnect structure (sidewall of 200) comprises a surface of a conductive feature which is in direct contact with the insulating encapsulant.
Chou doesn’t teach an upper surface of the interconnect structure comprises a surface of a conductive feature which is in direct contact with the insulating encapsulant.
However, Yu (fig. 18) teaches an upper surface of the interconnect structure ([0062], top of 316) comprises a surface of a conductive feature ([0062], top of 320, see fig. 13) which is in direct contact with the insulating encapsulant ([0061], 314]). Yu teaches that these conductive features may provide optional connections to conductive vias and redistributions ([0058], [0062]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor structure of Chou to include the conductive feature of Yu to provide additional connection points for conductive vias.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to Claim 1 above, and further in view of Chang (2025/0118718 A1; hereinafter Chang).
Regarding Claim 6, Chou (figs. 7-8) teaches the semiconductor structure of claim 1, wherein: the first semiconductor die (100, 200) further comprises a first bonding structure ([0035]-[0036], 234, 236, see fig. 7) having a first sidewall (sidewall of 234), the second semiconductor die (300) comprises a second bonding structure ([0037], 310, 312) bonded to the first bonding structure (234, 236) and having a second sidewall (sidewall of 310), and the insulating encapsulant extends along the first and second sidewalls.
Chou doesn’t teach the insulating encapsulant extends along the first and second sidewalls.
However, Chang (fig. 2) teaches the insulating encapsulant ([0023], 30) extends along the first ([0029], sidewall of 21) and second sidewalls ([0025], sidewall of 12). It is general knowledge to one of ordinary skill in the art that the insulating encapsulant of Chang provides additional protection and insulation along the sidewalls of the bonding structure while still providing the same protection and insulation as the insulating encapsulant of Chou.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to extend the insulating encapsulant alongside the bonding structure since there is a reasonable expectation of success. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chou and Chang as applied to Claim 6 above, and further in view of Yu.
Regarding Claim 7, Chou (figs. 7-8) teaches the semiconductor structure of claim 6, wherein the second semiconductor die (300) further comprises a semiconductor substrate (300) below the second bonding structure (310, 312), and an outer sidewall of the insulating encapsulant is substantially aligned with a sidewall of the semiconductor substrate of the second semiconductor die.
Chou doesn’t teach an outer sidewall of the insulating encapsulant is substantially aligned with a sidewall of the semiconductor substrate of the second semiconductor die.
However, Yu (fig. 18) teaches an outer sidewall of the insulating encapsulant ([0061], outer sidewall of 314) is substantially aligned with a sidewall of the semiconductor substrate ([0048], outer sidewall of 200) of the second semiconductor die (200). Yu also teaches that the semiconductor dies are formed to specific structural and functional requirements as needed by the system ([0049]). One of ordinary skill in the art could have second semiconductor die of Yu for the second semiconductor die of Chou and yielded the predictable results multiple integrated semiconductor dies.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the second semiconductor die of Yu for the second semiconductor die of Yu, since simple substitution of semiconductor dies for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to Claim 8 above, and further in view of Huang et al. (2023/0223311 A1; hereinafter Huang).
Regarding Claim 10, Chou doesn’t teach the semiconductor structure of claim 8, wherein the first and second portions of the insulating encapsulant are vertically separated from each other by a peripheral region of the first semiconductor die.
However, Huang (fig. 8) teaches the first ([0018], first portion comprising of 25, see annotated fig. 8) and second portions of the insulating encapsulant (second portion comprising of 25 in recess 221, see annotated fig. 8) are vertically separated from each other by a peripheral region (peripheral region) of the first semiconductor die ([0029], 21). Huang also teaches that this increases the bonding strength and avoids delamination ([0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor structure of Chou to include the recess of Huang to increase bonding strength and avoid delamination.
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Annotated Figure 8
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Chang and Yu.
Regarding Claim 12, Chou (figs. 7-8) teaches a semiconductor structure ([0014], 10, see fig. 1), comprising:
a first semiconductor die ([0014], 100, 200) comprising a functional region (functional region, see annotated fig. 8),
a seal ring region surrounding the functional region, and
a peripheral region (peripheral region, see annotated fig. 8) surrounding the seal ring region;
a second semiconductor die ([0014], 300) underlying and bonded to the first semiconductor die (100, 200); and
an insulating encapsulant ([0018], 140) disposed over the second semiconductor die (300), wherein the peripheral region (peripheral region) of the first semiconductor die (100, 200) is in physical contact with the insulating encapsulant (140) and comprises a sidewall substantially aligned with a sidewall of the second semiconductor die.
Chou doesn’t teach a seal ring region surrounding the functional region and a peripheral region surrounding the seal ring region.
However, Chang (fig. 2) teaches a seal ring region ([0063], outer portion of DR where GD is located) surrounding the functional region ([0063], center portion of DR where 222 is located) and a peripheral region ([0022], SLR) surrounding the seal ring region (GD). Chang also teaches that the seal ring region serves to block crack or moisture propagation ([0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor structure of Chou to include the seal ring region of Chang to block crack and moisture propagation.
Chou doesn’t teach an insulating encapsulant wherein a sidewall substantially aligned with a sidewall of the second semiconductor die.
However, Yu (fig. 18) teaches an insulating encapsulant ([0061], 314) wherein a sidewall (outer sidewall of 314) substantially aligned with a sidewall of the second semiconductor die ([0048], outer sidewall of 200). Yu also teaches that the semiconductor dies are formed to specific structural and functional requirements as needed by the system ([0049]). One of ordinary skill in the art could have second semiconductor die of Yu for the second semiconductor die of Chou and yielded the predictable results multiple integrated semiconductor dies.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the second semiconductor die of Yu for the second semiconductor die of Yu, since simple substitution of semiconductor dies for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
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Annotated Figure 8
Regarding Claim 13, Chou (figs. 7-8) teaches the semiconductor structure of claim 12, wherein the sidewall of the peripheral region (outer sidewall of 200 in peripheral region) of the first semiconductor die (100, 200) is substantially aligned with an outer sidewall of the insulating encapsulant (outer sidewall of 140), and an upper surface of the peripheral region (top surface of 200 in peripheral region) connected to the sidewall of the peripheral region (outer sidewall of 200 in peripheral region) is in physical contact with the insulating encapsulant (140).
Regarding Claim 14, Chou doesn’t teach the semiconductor structure of claim 12, wherein the first semiconductor die further comprises a conductive feature disposed in the peripheral region, and a surface of the conductive feature is in physical contact with the insulating encapsulant.
However, Yu (fig. 18) teaches the first semiconductor die ([0066], 300) further comprises a conductive feature ([0062], 320, see fig. 13) disposed in the peripheral region (peripheral region, see annotated fig. 18), and a surface of the conductive feature (top surface of 320 is in physical contact with the insulating encapsulant ([0061], 314). Yu teaches that these conductive features may provide optional connections to conductive vias and redistributions ([0058], [0062]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor structure of Chou to include the conductive feature of Yu to provide additional connection points for conductive vias.
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Annotated Figure 18
Regarding Claim 15, Chou (figs. 7-8) teaches the semiconductor structure of claim 12, wherein: the second semiconductor die (300) comprises a semiconductor substrate (300) and a bonding structure ([0035]-[0036], 234, 236, see fig. 7) over the semiconductor substrate (300) and bonded to the first semiconductor die (100, 200), and the sidewall of the peripheral region (outer right sidewall of 200 in peripheral region) of the first semiconductor die (100, 200) is substantially aligned with a sidewall of the bonding structure (outer sidewall of 234) which is laterally displaced from a sidewall of the semiconductor substrate (left sidewall of 300).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chou, Chang, and Yu as applied to Claim 12 above, and further in view of Huang.
Regarding Claim 16, Chou doesn’t teach the semiconductor structure of claim 12, wherein the insulating encapsulant comprises a first portion and a second portion vertically separated from each other by the peripheral region of the first semiconductor die.
However, Huang (fig. 8) teaches the insulating encapsulant ([0018], 25) comprises a first portion (first portion comprising of 25, see annotated fig. 8) and a second portion (second portion comprising of 25 in recess 221, see annotated fig. 8) vertically separated from each other by the peripheral region (peripheral region, see annotated fig. 8) of the first semiconductor die ([0029], 21).Huang also teaches that this increases the bonding strength and avoids delamination ([0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor structure of Chou to include the recess of Huang to increase bonding strength and avoid delamination.
Regarding Claim 17, Chou doesn’t teach the semiconductor structure of claim 12, wherein the first portion of the insulating encapsulant is wider than the second portion of the insulating encapsulant.
However, Huang (fig. 8) teaches the first portion of the insulating encapsulant ([0018], first portion comprising of 25, see annotated fig. 8) is wider than the second portion of the insulating encapsulant (second portion comprising of 25 in recess 221, see annotated fig. 8). Huang also teaches that this increases the bonding strength and avoids delamination ([0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor structure of Chou to include the recess of Huang to increase bonding strength and avoid delamination.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to Claim 21 above, and further in view of Yu.
Regarding Claim 23, Chou (figs. 7-8) teaches the semiconductor structure of claim 21, wherein a sidewall of the insulating encapsulant (sidewall of 140) is substantially coplanar with a sidewall of the interconnect structure (sidewall of 200) and a sidewall of the second semiconductor die.
Chou doesn’t teach a sidewall of the insulating encapsulant ([0061], outer sidewall of 314) is substantially coplanar with a sidewall of the second semiconductor die ([0048], outer sidewall of 200). Yu also teaches that the semiconductor dies are formed to specific structural and functional requirements as needed by the system ([0049]). One of ordinary skill in the art could have second semiconductor die of Yu for the second semiconductor die of Chou and yielded the predictable results multiple integrated semiconductor dies.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the second semiconductor die of Yu for the second semiconductor die of Yu, since simple substitution of semiconductor dies for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yu et al. (2020/0043896 A1) teaches semiconductor dies bonded together with a recess in a bonding layer. See fig. 7 and paragraphs [0012]-[0031].
Odnoblyudov et al. (2021/0135067 A1) teaches semiconductor dies bonded together with an insulating encapsulant along the bonding region. See fig. 5 and paragraphs [0022]-[0027].
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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