DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 04/23/2026. Claims 2-6, 8-10, 12, 14, 16 and 17 have been cancelled. Claims 18-29 have been added new. Claims 1, 7, 11, 13, 15 and 18-29 are now pending in the application, of which Claims 1 and 13 are independent.
Continuity/ Priority Information
The present Application 18595877 filed 03/05/2024 claims foreign priority to JAPAN, Application 2023-050712, filed 03/28/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments, see Amendment/ Remarks filed 04/23/2026, with respect to the rejection of Claims 1, 7, 11, 13, 15 and 18-29 under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (Pub. No. US 20210027830), have been fully considered but they are not persuasive, as set forth in the present office action.
Claims objections for minor informalities and rejections under 112b, second paragraph, are withdrawn due to the amendment to the Claims.
Applicant argues that KIM does not describe obtaining "read error information" that includes "respective error information corresponding to respective stored data values of the memory cells" and therefore, Kim fails to describe adjusting the sensing-related parameter based on "a relationship between the respective error information corresponding to the respective stored data values” as recited in amended independent claims 1 and 13.
In response to Applicant arguments, KIM discloses, FIG. 16 the semiconductor memory device of FIG. 2 in a read operation. Para. [0164] In the read operation, the ECC engine 400 performs a scrubbing operation by performing an ECC decoding on the codeword RCW, correcting at least one error in the codeword RCW and writing back the corrected data in a memory location in which a sub-page is stored. When the least one error is detected during performing the scrubbing operation, the ECC engine 400 provides the control logic circuit 210 with the error information EINF including the error generation signal EGS whenever the error is detected.
Also, Referring to FIG. 12, [0147] The encoding/decoding logic 420, in the read operation, the data corrector 460 corrects an error in the read data RMD based on the syndrome data SDR from the encoding/decoding logic 420 to provide corrected main data C_MD and may provide the control logic circuit 210 with the error information EINF including the error generation signal EGS if the error is detected in the read data RMD.
Clearly, the error information EINF detected in the read data RMD corresponds to stored data values of the memory cells, i.e. MD main data stored in the memory blocks 311-313 of the memory cell array 300a, as disclosed by Kim, Figs 12 and 16.
Applicant further argues that Kim does not describe the recited comparison between the respective error information corresponding to the respective stored data values and a predetermined value.
In response to Applicant arguments, Kim's discloses para. [0171] The fifth column 585 stores the flag information FG The flag information FG indicates whether the error information of the corresponding page is initially written into the error log register 580. When the error information of the corresponding page is initially written into the error log register 580, the flag information FG has a first logic level (e.g., 0). In an embodiment, if the flag information FG of a page has a second logic level (e.g., 1), the page previously had error information.
Clearly, Kim's disclosure is functionally equivalent to the Claimed comparison, because both features perform the same function, i.e. generating an error flag information “FG”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 11, 13, 15 and 18-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (Pub. No. US 20210027830).
Regarding independent Claims 1 and 13, KIM discloses semiconductor memory devices and methods, comprising:
a memory cell array comprising a plurality of memory cells connected to one of the plurality of word lines and the bit line; and a sense amplifier connected to the bit line; [0046] FIG. 2 illustrates a semiconductor memory device in FIG. 1. The memory cell array 300 may include a plurality of memory cells MCs coupled to each word-line WL and each bit-line BL and a “sense amplifier” BLSA 280 coupled to the bit-line BL and a complementary bit-line BLB.
an adjustment unit configured to obtain read error information associated with read operations performed on the memory cells, wherein the read error information includes respective error information corresponding to respective stored data values of the memory cells; Referring to FIG. 12, [0147] The encoding/decoding logic 420, in the read operation, the data corrector 460 corrects an error in the read data RMD based on the syndrome data SDR from the encoding/decoding logic 420 to provide corrected main data C_MD and may provide the control logic circuit 210 with the error information EINF including the error generation signal EGS if the error is detected in the read data RMD.
Para. [0164] FIG. 16. In the read operation of the memory device, when the least one error is detected during performing the scrubbing operation, the ECC engine 400 provides the control logic circuit 210 with the error information EINF including the error generation signal EGS whenever the error is detected.
adjust a sensing-related parameter related to a condition of a sensing operation of the sense amplifier based on at least one of: (i) a relationship between the respective error information corresponding to the respective stored data values; and (ii) a comparison between (a) the respective error information corresponding to the respective stored data values and (b) a predetermined value. [0052] The control logic circuit 210 may accumulate the error information EINF associated with a page of a sub-page corresponding to an address associated with an error based on the error information EINF and may record the accumulated error information in the EPIR 580 as an error pattern information EPI. [0053] The voltage generator 700 may generate the driving voltages VLA1 and VLA2 and the pre-charge voltage VBL based on voltages VCC and VSS and may adjust voltage levels of at least one of the driving voltages VLA1 and VLA2 and the pre-charge voltage VBL based on the third control signal CTL13 and may provide the driving voltages VLA1 and VLA2 and the pre-charge voltage VBL to the sense amplifier 280.
Regarding Claim 7, KIM discloses the sense amplifier is a cross-coupled latch-type sense amplifier comprising two NMOS transistors and two PMOS transistors connected between a pair of bit lines, and……. a balance voltage between the pair of bit lines. [0073] Referring to FIG. 5, the sense amplifier 280 may include a sense amplifying circuit 280, a latch circuit 283 and a switching circuit including a bit-line switch SWa, a complementary bit-line switch SWb, a power witch SW10, and first to sixth switches SW1 to SW6. [0075] The sense amplifying circuit 281 is connected to a first sensing signal node LA1 and a second sensing signal node LAB1 and includes p-channel metal-oxide-semiconductor (PMOS) transistors P11 and P12 “NMOS transistors” and n-channel metal-oxide-semiconductor (NMOS) transistors N11 and N12.
Regarding Claim 11, 26, KIM discloses, during the read operations, the adjustment unit is configured to select the memory cells according to a predetermined selection sequence such that the selected memory cells are connected to different word lines and bit lines. [0052] The control logic circuit 210 may accumulate the error information EINF associated with a page of a sub-page corresponding to an address associated with an error based on the error information EINF and may record the accumulated error information in the EPIR 580 as an error pattern information EPI. The accumulated error information (i.e., the pattern information EPI) in the EPIR 580 may represent error pattern or tendency of a page in which the errors occur.
Regarding Claim 15, KIM discloses the semiconductor memory device comprises a row decoder, and a column decoder, and the device is a volatile memory. [0045] Referring to FIG. 2, the semiconductor memory device 200 may include the control logic circuit 210, the memory cell array 300, a row decoder 261, and a column decoder 271.
Regarding Claims 18, 19, 21, 22, 24, 25, KIM discloses comprises among others, a plurality of counters configured to accumulate the first error information and the second error information, generate an adjustment signal for adjusting the sensing-related parameter, and provides a warning signal to a memory controller.
[0052] The control logic circuit 210 may accumulate the error information EINF associated with a page of a sub-page corresponding to an address associated with an error based on the error information EINF and may record the accumulated error information in the EPIR 580 as an error pattern information EPI. The accumulated error information (i.e., the pattern information EPI) in the EPIR 580 may represent error pattern or tendency of a page in which the errors occur. The control logic circuit 210 may control the voltage generator 700 to adjust voltage levels of at least one of the driving voltages VLA1 and VLA2 and a pre-charge voltage VBL. The pre-charge voltage may be used for pre-charging the bit-line BL and the complementary bit-line BLB.
“warning signal” [0171] The fifth column 585 stores the flag information FG The flag information FG indicates whether the error information of the corresponding page is initially written into the error log register 580.
Regarding Claim 20, KIM discloses an ECC unit including a check digit calculation unit configured to generate checking data for deriving the expected-value data information. [0145] Referring to FIG. 12, the ECC engine 400 may include a multiplexer 410, an encoding/decoding logic 420, a buffer unit 440 and a data corrector 460. The buffer unit 440 may include first through fourth buffers 441-444.
Regarding Claim 23, KIM discloses the memory cell array further comprises at least one spare cell; and after the sensing-related parameter is adjusted to the condition, the semiconductor memory device performs a redundancy repair operation using the at least one spare cell on memory cells associated with read errors corresponding to the sensing- related parameter. [0157] Referring to FIG. 15, the memory cell array 300a includes a normal cell array NCA and a redundancy cell array RCA. The redundancy cell array RCA includes at least a second memory block 314. The second memory block 314 is for ECC and/or redundancy repair. Since the second memory block 314 for ECC and/or redundancy repair “redundancy repair operation” is used for ECC, data line repair and block repair to repair ‘fail’ cells generated in the first memory blocks 311-313, the second memory block 314 is also referred to as an EDB block.
Regarding Claims 27-29, KIM discloses the control method further comprises: accumulating the first error information and the second error information, respectively, and generating an adjustment signal for adjusting the sensing-related parameter, until the sensing-related parameter reaches a condition within a predefined range. [0009] Accordingly, the control logic circuit generates error pattern information by accumulating error information obtained by a result of ECC decoding and the control logic circuit controls the voltage generator to adjust voltage levels of driving voltages provided to sense amplifiers based on the error pattern information such that operating margin of the sense amplifier may be increased. Therefore, the semiconductor memory device may enhance performance.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571) 272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: May 8, 2026
Final Rejection 20260507
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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