DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 12/15/2025. Claims 2 and 4 are cancelled. Claim 15-17 are new.
Claims 1, 3 and 5-17 are pending in the Application, of which Claims 1, 13 and 14 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/2025 has been entered.
Continuity/ Priority Information
The present Application 18595877 filed 03/05/2024 claims foreign priority to JAPAN, Application 2023-050712, filed 03/28/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments, see Amendment/ Remarks filed 12/15/2025, with respect to the rejection of Claims 1, 3 and 5-17 under 35 U.S.C. 102(a)(1) as being anticipated by Cunningham et al. (Pub. No. US 20140059398), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of KIM et al. (Pub. No. US 20210027830) Pub. Date: 2021-01-28, as set forth in the present office action.
The Examiner agrees with Applicant’s arguments that Cunningham fails to teach "the memory cell array comprises a spare cell, and after the adjustment unit adjusts the value of the parameter so that the number of erroneously-read memory cells is the minimum, the semiconductor memory device uses the spare cell to perform a redundancy repair operation on the memory cells with reading errors corresponding to the parameter" as recited in amended claims 1, 13 and 14.
However, under a new ground(s) of rejection, KIM (US 20210027830) discloses the above limitation, as described further in the office action below.
Claim Objections
Claims 1, 3 and 5-17 are objected to because of the following informalities:
Claim 1, “wherein the adjustment unit adjusts a value of the parameter until the number of erroneously-read memory cells is the minimum”.
then the adjustment unit adjusts the value of the parameter until the number of erroneously-read memory cells is the minimum”.
“and after the adjustment unit adjusts the value of the parameter until the number of erroneously-read memory cells is the minimum”.
Claims 13 and 14, similar amendments of Claim 1 should be made where applicable in Claims 13 and 14. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3 and 5-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 13 and 14, the limitation “when there is a reading error in reading operations of "1" and "0" data performed on the memory cell reads the "1" and "0" data, the adjustment unit changes the parameter while counts the number of memory cells with reading errors in the reading operation of the "1" data ….. and of the "0" data” is indefinite. It is unclear whether both logic levels "1" and "0" indicate two different type of errors, such as "1" indicates error due to open and "0" indicates error due to short, because of a defective memory cell. Alternatively, whether "1" is normal cell with no error and "0" is a defective cell with error. It is well-known in the area of memory testing using an error detection method, that "1" indicates error due to a defect in a memory cell and "0" indicates no error with normal operating mode.
Any claim not specifically mentioned above is rejected because of its dependency on a rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3 and 5-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (Pub. No. US 20210027830).
Regarding independent Claims1, 13 and 14, KIM discloses semiconductor memory devices and methods, comprising:
a memory cell array comprising a plurality of memory cells connected to one of the plurality of word lines and the bit line; a sense amplifier connected to the bit line; [0046] FIG. 2 illustrates a semiconductor memory device in FIG. 1. The memory cell array 300 may include a plurality of memory cells MCs coupled to each word-line WL and each bit-line BL and a sense amplifier BLSA 280 “sense amplifier” coupled to the bit-line BL and a complementary bit-line BLB.
counting the number of erroneously-read memory cells “having different read values from expected values”; [0052] The control logic circuit 210 may accumulate the error information EINF associated with a page of a sub-page corresponding to an address associated with an error based on the error information EINF and may record the accumulated error information in the EPIR 580 as an error pattern information EPI.
wherein the adjustment unit adjusts a value of the parameter, and the number of erroneously-read memory cells is the minimum. [0052] The control logic circuit 210 may control the voltage generator 700 to adjust voltage levels of at least one of the driving voltages VLA1 and VLA2 and a pre-charge voltage VBL.
[0053] The voltage generator 700 may generate the driving voltages VLA1 and VLA2 and the pre-charge voltage VBL based on voltages VCC and VSS and may adjust voltage levels of at least one of the driving voltages VLA1 and VLA2 and the pre-charge voltage VBL based on the third control signal CTL13 and may provide the driving voltages VLA1 and VLA2 and the pre-charge voltage VBL to the sense amplifier 280.
Wherein, when there is a reading error in reading operations of “1” and “0” ……….,the greater number of memory cells is set as the number of erroneously-read memory cells, and then the value of the parameter is adjusted so that the number of erroneously-read memory cells is the minimum.
[0050] The ECC engine 400 may perform an ECC decoding on the codeword CW to provide the main data MD to the data I/O buffer 296 in a read operation and may provide the control logic circuit 210 with error information EINF including error generation signal EGS if an error is detected in the read data based on a result of the ECC decoding. The error information EINF may include information on a number of errors and position in which the errors occur.
[0052] The accumulated error information (i.e., the pattern information EPI) in the EPIR 580 may represent error pattern or tendency of a page in which the errors occur. The control logic circuit 210 may control the voltage generator 700 to adjust voltage levels of at least one of the driving voltages VLA1 and VLA2 and a pre-charge voltage VBL.
the semiconductor memory device uses the spare cell to perform a redundancy repair operation on the memory cells with reading errors corresponding to the parameter. [0157] Referring to FIG. 15, the memory cell array 300a includes a normal cell array NCA and a redundancy cell array RCA. The first memory blocks 311-313 are memory blocks determining a memory capacity of the semiconductor memory device 200. The second memory block 314 is for ECC and/or redundancy repair. Since the second memory block 314 for ECC and/or redundancy repair is used for ECC, data line repair and block repair to repair ‘fail’ cells generated in the first memory blocks 311-313, the second memory block 314 is also referred to as an EDB block.
Regarding Claim 3, KIM discloses if one of the number of memory cells with errors in the reading operation of the "1" data and the number of memory cells with errors in the reading operation of the "0" data is greater than or equal to a predetermined value, the adjustment sets the number of memory cells as the number of erroneously-read memory cells without comparison. [0043] FIG. 1. The control logic circuit 210 may control the at least one voltage generator 700 to adjust voltage levels of driving voltages VLA1 and VLA2 based on error pattern information including the error information. The control logic circuit 210 may control the voltage generator 700 to increase an operating margin of the sense amplifier 280 during the sense amplifier 280 performs sensing/restore operation based on the adjusted driving voltages VLA1 and VLA2.
Regarding Claims 5, KIM discloses the semiconductor memory device uses the spare cells to perform a redundancy repair operation on the memory cells with reading errors corresponding to the parameter. [0157] Referring to FIG. 15, the memory cell array 300a includes a normal cell array NCA and a redundancy cell array RCA “spare cells”. The first memory blocks 311-313 are memory blocks determining a memory capacity of the semiconductor memory device 200. The second memory block 314 “spare cells” is for ECC and/or redundancy repair.
Regarding Claims 6-7, KIM discloses wherein the sense amplifier is a cross-coupled latch-type sense amplifier consisting of two NMOS transistors and two PMOS transistors connected between a pair of bit lines.
[0072] FIG. 5 illustrating an example of the sense amplifier in FIG. 3. [0073] Referring to FIG. 5, the sense amplifier 280 may include a sense amplifying circuit 280, a latch circuit 283 and a switching circuit including a bit-line switch SWa, a complementary bit-line switch SWb, a power witch SW10, and first to sixth switches SW1 to SW6. [0075] The sense amplifying circuit 281 is connected to a first sensing signal node LA1 and a second sensing signal node LAB1 and includes p-channel metal-oxide-semiconductor (PMOS) transistors P11 and P12 “NMOS transistors” and n-channel metal-oxide-semiconductor (NMOS) transistors N11 and N12.
Regarding Claim 8, KIM discloses the adjustment unit comprises a first comparator, ……, and the first comparator generates error information from the reading data information, and the error information specifies which memory cell has the reading error in the reading operation of the “1” data or the “0” data of the memory cell. [0050] The ECC engine 400 may perform an ECC decoding on the codeword CW to provide the main data MD to the data I/O buffer 296 in a read operation and may provide the control logic circuit 210 with error information EINF including error generation signal EGS if an error is detected in the read data based on a result of the ECC decoding. The error information EINF may include information on a number of errors and position in which the errors occur.
Regarding Claims 9-11, KIM discloses the adjustment unit counts the number of memory cells with reading errors …….. and when one of the number of memory cells with errors in the reading operation of the “1” data and the number of memory cells with errors in the reading operation of the “0” data is greater than a predetermined value, a warning is issued. [0052] The control logic circuit 210 may accumulate the error information EINF associated with a page of a sub-page corresponding to an address associated with an error based on the error information EINF and may record the accumulated error information in the EPIR 580 as an error pattern information EPI. The accumulated error information (i.e., the pattern information EPI) in the EPIR 580 may represent error pattern or tendency of a page in which the errors occur.
Regarding Claim 12, KIM discloses wherein the semiconductor memory device is a volatile memory. Referring to FIG. 1, [0039] In some embodiments, the semiconductor memory device 200 is a memory device including dynamic memory cells such as a dynamic random access memory (DRAM), double data rate 4 (DDR4) synchronous DRAM (SDRAM), a DDRS SDRAM a low power DDR4 (LPDDR4) SDRAM or a LPDDR5 SDRAM.
Regarding Claims 15-17, KIM discloses the semiconductor memory device further comprises a row decoder; and a column decoder. [0045] Referring to FIG. 2, the semiconductor memory device 200 may include the control logic circuit 210, the memory cell array 300, a row decoder 261, and a column decoder 271.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 22, 2026
Non-Final Rejection 20260121
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV