Prosecution Insights
Last updated: April 19, 2026
Application No. 18/596,404

3D IC POWER GRID

Non-Final OA §103§112
Filed
Mar 05, 2024
Examiner
REAMES, MATTHEW L
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
95%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
827 granted / 1076 resolved
+8.9% vs TC avg
Strong +18% interview lift
Without
With
+17.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
32 currently pending
Career history
1108
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
40.7%
+0.7% vs TC avg
§102
20.0%
-20.0% vs TC avg
§112
33.8%
-6.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1076 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of species in the interview on 10/22/2025 is acknowledged. Claims 9-10 should not be withdrawn. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the Figure 5 does not show the features of claims 8-10 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Specifically, there is no additional first and second TSV and no power distribution structure. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Item 512 is not listed in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 8-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Applicant does not have support for further comprising a power distribution structure in the top die, the power distribution structure comprising: a first Through-Silicon Via (TSV) connected to a first package bump; a first ladder structure connected to the first TSV, a second TSV connected to a second package bump. Instead figure 5 states Figure 5 illustrates an integrated circuit device in accordance consistent with the present disclosure, which in some embodiments may include a system on an integrated chip (SoIC) 500. As shown in Figure 5, SoIC 500 may comprise a bottom wafer 502, a top wafer 504, a bottom die 506, top die(s) 508, and access points (APs) 510. Access points 510 may be used for testing. SoIC 500 may further comprise a Bonding Pad Via (BPV) 514, a Bonding pad metal (BPM) 516, a Top Metal 1 (TM1) layer 518, a Top Metal 2 (TM2) layer 520, and a TSV 522. SoIC 500 may be provided with a long TSV 522. This long TSV 522 may directly go to TM1 layer 518 through silicon, where as a short TSV may only penetrate silicon and through the first metal layer. This long TSV (522) structure also reduces the IR drop issue caused by short TSVs. With this embodiment, the power source current may directly reach to the inter die interface quickly through long TSV 522 and there it can distribute power to top die 508 and bottom die 506. There is only one TSV depicted in figure 5. Further there is only one power terminal PG. Assuming arguendo that PG connects to the ladder in figure 5 via a TSV there is still a missing TSV that corresponds to the power distribution. However, this is not a requirement and the ladder can be connected to a redistribution layer. Further there is only on ladder in figure 5 and there is no indication that it is part of the This interpretation also contradicts the embodiment of figure 5 description which states power distribution is handled by TSV 522 and not the ladder structure. The examiner will point out though this recitation that power distribution is handled by 522 is inconsistent with the rest of the disclosure since TSV 522 is connected to the signal bump and not the power bump PG and in all the other embodiments the power distribution is handled by the ladder structure. Regardless applicant does not teach two additional TSV and does not teach two ladder structures. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 3 Applicant recites and a through silicon via connected to the top metal two layer, wherein the through silicon via directly goes to the top metal one layer through silicon. It is unclear where the silicon is and if it relates to the one of the wafers or some other structure not claimed. As to claim 3, recites ; a top metal two layer connected to the top metal one layer; and a through silicon via connected to the top metal two layer, wherein the through silicon via directly goes to the top metal one layer through silicon. It is unclear what is meant by wherein the through silicon via directly goes to the top metal one layer since the TSV is connected to top metal layer 2 and not top metal layer one see claim 3 (a through silicon via connected to the top metal two layer) and see also figure 5 it 522 contacts 520 which is top metal layer two. Item 522 does not go to item 518 top metal layer one. As to claim 8-10 it is unclear where the first and second TSV are in relation to the wafer or what makes them Through silicon vias. As to claim 7, the phrase face to face is unclear since applicant has not established the device has a face. As to claim 9, claim 9 recites wherein the power distribution structure is configured to supply power to the top die and to the bottom die. This is unclear since it sets forth a function with no corresponding structure MPEP 2173.05g functional language. Further it is in consistent with the specification that states power is provided via the TSV 522 and not a TSV connected to a ladder structure. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin 20150221785 in view of Tsai 20150348917. As to claim 3, Lin teaches A system on an integrated chip, comprising: a bottom wafer item (figures 104); a top wafer (204 figures); a bottom die placed on the bottom wafer (items 107-146 figure 1a see figure 2D for final structure); a top die placed on the top wafer (items 207-246 figure 1a figure 2D final device); a bonding pad via formed in the bottom die (item 400 corresponding to 144 corresponding to 124), a bonding pad metal formed on the bonding pad via (item 144 paragraph 21), a top metal one layer connected to the bonding pad metal (item 244 or the conductive feature 224); a top conductive two layer connected to the top metal one layer (item 224 or item 244); and a through silicon via connected to the top conductive two layer (item 600), wherein the through silicon via directly goes to the top metal one layer through silicon (600 either goes the conductive feature item 224 or goes to item 244 through 224). Lin does not state the conductive features are metal Tsai teaches the conductive features in the device maybe metal (items 108 paragraph 35). It would therefore have been obvious to one of ordinary skill in the art at the time of filing to provide the conductive layer in item 122 and 222 items 124 and 224) as a metal specifically copper to provide a low resistance material used conventionally at the time of filing to improve device performance by providing low resistance connection to devices. b. As to claim 4, Lin teaches further comprising access points in the top die and the bottom die (the vias 400 and 600). c. As to claim 5-6. Lin teaches “functional” elements in the top die and lower die the wiring 114 is functional as well as the transistors (paragraph 12). d. As to claim 7, Lin wherein the top die is stacked on the bottom die in a face-to-face configuration Back end to back-end bonding (BEOL to BEOL bonding). Claim Rejections - 35 USC § 103 Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin 20150221785 in view of Tsai 20150348917. In further view of Chu cited in on ids (20170186732). As to claim 8, Lin and Tsai do not teach a first Through-Silicon Via (TSV) connected to a first package bump; a first ladder structure connected to the first TSV, a second TSV connected to a second package bump, and a second ladder structure connected to the second TSV. Chu teaches a structure comprising a backside pads/bumps (paragraph 42 item 402 top part) and TSVs corresponding to the pads (item 402 in 148 or 412 figure 4b 4c 14b and C as ). a first ladder structure connected to the first TSV (item 146d), a second TSV (either 402 in 148 or 412 corresponding to 146a-c) a connected to a second package bump(item 402), and a second ladder structure connected to the second TSV (item 146a-146d). Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide multiple ladder structures for sealing the device from cracks and providing TSV for the multiple ladder structures to aid with electrical contact as suggest by Chu (paragraph 16 and 27). b. As to claim 9, In so far as definite Chu suggests wherein the power distribution structure is configured to supply power to the top die and to the bottom die (paragraph 16 and 27). c. As to claim 10, Chu teaches wherein the power distribution structure passes through the top die (see figures it pass through the BEOL and FEOL of the die which corresponds to applicants’ definition of a die. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsunemi (20150137238) teaches two TSVs on connected to a ladders structure and another connected to ground for heat flow figure 16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW L. REAMES/ Primary Examiner Art Unit 2896 /MATTHEW L REAMES/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Mar 05, 2024
Application Filed
Oct 22, 2025
Examiner Interview (Telephonic)
Oct 27, 2025
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604593
LED Structure, LED Device and Method of Manufacturing LED Structure
2y 5m to grant Granted Apr 14, 2026
Patent 12598934
METHOD OF MANUFACTURING STRUCTURE HAVING MULTI METAL LAYERS
2y 5m to grant Granted Apr 07, 2026
Patent 12593620
TECHNOLOGIES FOR SCALABLE SPIN QUBIT READOUT
2y 5m to grant Granted Mar 31, 2026
Patent 12588299
SEMICONDUCTOR LIGHT RECEPTION ELEMENT
2y 5m to grant Granted Mar 24, 2026
Patent 12588191
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
95%
With Interview (+17.8%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 1076 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month