0W20/20 OR H10W90/00 OR H10W20/2134).cpc.
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the silicon on the wafer must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The embodiment of figure 5 is not disclosed to any detail specifically there is no discussion of item 512 or the wafer comprising a silicon layer. Further there is no label an no discussion of specific elements.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 3-10 and 22-33 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
a. Claim 3 22 29 are assumed to be drawn to figure 5 from the previous election and require through silicon via connected to the top metal two layer, wherein the through silicon via directly goes to the top metal one layer through silicon on the top wafer and the top die. However, has never set forth a separate silicon layer on the wafer. Figure 5 is an SOIC, paragraph 9 Small Outline Integrated Circuit. Applicant has never set forth that there is a separate silicon layer on the wafer. It appears there might be due to the line but there is no discussion of this element Further a line does not necessarily indicate that there is a new element. Thus since the original disclosure is silent, Applicant does not have support for a separate wafer and separate silicon layer.
b. As to claim 10, 28, and 33 Applicant does not have support for wherein the power distribution structure passes through the top die. Specifically, applicant does not teach the power distribution through the silicon layer (sic wafer) in the elected embodiment of figure 5 it stops at the top of the wafer/silicon layer.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-10 and 22-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a. As to claim 3 22 and 29, recitation of a through silicon via connected to the top metal two layer, wherein the through silicon via directly goes to the top metal one layer through silicon on the top wafer and the top die is unclear since applicant does not structurally link the metal layer and the silicon in how they interrelate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-7 and 22-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin 20150221785 in view of Tsai 20150348917.
a. As to claims 3, 4 and 22, Lin teaches A system on an integrated chip, comprising: a bottom wafer item (figures top portions of item 104); a top wafer (bottom portion of item 204 figures); a bottom die placed on the bottom wafer (items 107-146 figure 1a see figure 2D for final structure); a top die placed on the top wafer (items 207-246 figure 1a figure 2D final device); a bottom bonding pad via formed in the bottom die (item 400 corresponding to 144 corresponding to 124), a bottom bonding pad metal formed on the bonding pad via (item 144 paragraph 21 on does not require direct connection), a top metal one layer connected to the top bonding pad metal (item 214); a top conductive two layer connected to the top metal one layer (item 224); and a through silicon via connected to the top conductive two layer (item 600), wherein the through silicon via directly goes to the top metal one layer through silicon (600 either goes directly to conductive feature item 224). Lin further teaches a top bonding pad item 244 and the bottom pad is connected to top pad figure 1a. Lin teaches further comprising access points in the top die and the bottom die (the others of vias 400 and 600). Lin teaches 400 and 600 go through the active silicon layer portion on other part of item 103 and the active silicon layer of item 204 on the other part of 204 not part of the wafer and the 1st conductive layer item 114 or 214)
Lin does not state the conductive features are metal
Tsai teaches the conductive features in the device maybe metal (items 108 paragraph 35).
It would therefore have been obvious to one of ordinary skill in the art at the time of filing to provide the conductive layer in item 122 and 222 items 124 and 224) as a metal specifically copper to provide a low resistance material used conventionally at the time of filing to improve device performance by providing low resistance connection to devices.
Lin in view of Tsai would teach wherein the bottom bonding pad metal is connected to a top bonding pad metal formed in the top die since Lin suggests metal.
c. As to claims 5-6, 23-24, Lin teaches “functional” elements in the top die and lower die the wiring 114 is functional as well as the transistors (paragraph 12).
d. As to claims 7, and 25 Lin wherein the top die is stacked on the bottom die in a face-to-face configuration Back end to back-end bonding (BEOL to BEOL bonding).
Claim(s) 8-10, 26-28 and 29-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin 20150221785 in view of Tsai 20150348917. In further view of Chu cited in on ids (20170186732).
a. As to claims 8, and 26, Lin and Tsai do not teach further comprising a power distribution structure in the top die, the power distribution structure comprising: a second top bonding pad metal formed in the top die, wherein the second top bonding pad metal is connected to a second bonding pad metal of the bottom die; a second top bonding pad via formed in the top die and connected to the second top bonding pad metal a ladder structure connected to the second top bonding pad via;
Chu teaches a structure : a second top bonding pad metal formed in the top die figure 5 and 10 top item 138 at item 134) , wherein the second top bonding pad metal is connected to a second bonding pad metal of the bottom die (the corresponding item 138 of the other die figure 5 at item 134); a second top bonding pad via formed in the top die and connected to the second top bonding pad metal (item 140) a ladder structure connected to the second top bonding pad via (item 108 figure 10).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide multiple ladder structures for sealing the device from cracks and providing TSV for the multiple ladder structures to aid with electrical contact as suggest by Chu (paragraph 16 and 27).
b. As to claims 9, and 27, Chu suggests wherein the power distribution structure is configured to supply power to the top die and to the bottom die (paragraph 16 and 27).
c. As to claims 10 and 28, Chu teaches wherein the power distribution structure passes through substantially all of the top die (see figures it pass through the BEOL and FEOL of the die which corresponds to applicants’ definition of a die).
d. As to claims 29 and 30, Lin teaches A system on an integrated chip, comprising: a bottom wafer item (figures top portions of item 104); a top wafer (bottom portion of item 204 figures); a bottom die placed on the bottom wafer (items 107-146 figure 1a see figure 2D for final structure); a top die placed on the top wafer (items 207-246 figure 1a figure 2D final device); a bottom bonding pad via formed in the bottom die (item 400 corresponding to 144 corresponding to 124), a bottom bonding pad metal formed on the bonding pad via (item 144 paragraph 21 on does not require direct connection), a top metal one layer connected to the top bonding pad metal (item 214); a top conductive two layer connected to the top metal one layer (item 224); and a through silicon via connected to the top conductive two layer (item 600), wherein the through silicon via directly goes to the top metal one layer through silicon (600 either goes directly to conductive feature item 224). Lin further teach a top bonding pad item 244 and the bottom pad is connected to top pad figure 1a. Lin teaches further comprising access points in the top die and the bottom die (the others of vias 400 and 600). Lin teaches 400 and 600 go through the active silicon layer portion on other part of item 103 and the active silicon layer of item 204 on the other part of 204 not part of the wafer and the 1st conductive layer item 114 or 214)
Lin does not state the conductive features are metal
Tsai teaches the conductive features in the device maybe metal (items 108 paragraph 35).
It would therefore have been obvious to one of ordinary skill in the art at the time of filing to provide the conductive layer in item 122 and 222 items 124 and 224) as a metal specifically copper to provide a low resistance material used conventionally at the time of filing to improve device performance by providing low resistance connection to devices.
Lin in view of Tsai would teach wherein the bottom bonding pad metal is connected to a top bonding pad metal formed in the top die since Lin suggests metal.
Lin and Tsai do not teach further comprising a power distribution structure in the top die, the power distribution structure comprising: a second top bonding pad metal formed in the top die, wherein the second top bonding pad metal is connected to a second bonding pad metal of the bottom die; a second top bonding pad via formed in the top die and connected to the second top bonding pad metal a ladder structure connected to the second top bonding pad via;
Chu teaches a structure : a second top bonding pad metal formed in the top die figure 5 and 10 top item 138 at item 134) , wherein the second top bonding pad metal is connected to a second bonding pad metal of the bottom die (the corresponding item 138 of the other die figure 5 at item 134); a second top bonding pad via formed in the top die and connected to the second top bonding pad metal (item 140) a ladder structure connected to the second top bonding pad via (item 108 figure 10);
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide multiple ladder structures for sealing the device from cracks and providing TSV for the multiple ladder structures to aid with electrical contact as suggest by Chu (paragraph 16 and 27).
e. As to claim 31 Lin teaches “functional” elements in the top die and lower die the wiring 114 is functional as well as the transistors (paragraph 12).
f. As to claim 32, Chu suggests wherein the power distribution structure is configured to supply power to the top die and to the bottom die (paragraph 16 and 27).
g. As to claim 33, Chu teaches wherein the power distribution structure passes through substantially all of the top die (see figures it pass through the BEOL and FEOL of the die which corresponds to applicants’ definition of a die).
Response to Arguments
Applicant’s arguments with respect to claim(s) 3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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