DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9-12 and 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US Pub. 2018/0061835; hereinafter “Yang”).
Regarding Claim 1, Yang discloses a memory cell, comprising: a transistor T1 including a source region 28, channel region 26 and drain region 30 in a nanowire structure (page 2, paragraph 27; see fig. 2); and a capacitive device 38 on the transistor T1 (page 2, paragraph 30; see fig. 2) and including a first conductor 42 (inner node; page 2, paragraph 30) in the nanowire structure (see fig. 2).
Regarding Claim 9, Yang discloses wherein the source region 28, channel region 26 and drain region 30 of the transistor T1 comprise a first diameter (see fig. 2) and the first conductor 42 of the capacitive device 38 comprises a second diameter greater than the first diameter (see fig. 2).
Regarding Claim 10, Yang discloses a method of forming a memory cell, the method comprising: forming a source region 28, channel region 26 and drain region 30 of a transistor T1 in a nanowire structure (page 2, paragraph 27; see fig. 2); and forming a first conductor 42 (inner node; page 2, paragraph 30) of a capacitive device 38 on the source region 28, channel region 26 and drain region 30 in the nanowire structure (page 2, paragraph 30; see fig. 2).
Regarding Claim 11, Yang discloses wherein the forming of the source region 28, channel region 26 and drain region 30 comprises stacking the source region 28, channel region 26 and drain region 30 in a first direction (vertical direction) (see fig. 2).
Regarding Claim 12, Yang discloses further comprising: forming a gate structure 14 of the transistor T1 around the channel region 26 (page 2, paragraph 26; see fig. 2), wherein the gate structure 14 comprises a portion of a word line WL (page 2, paragraph 24) extending lengthwise in a second direction (lateral direction) perpendicular to the first direction (vertical direction) (see fig. 2).
Regarding Claim 15, Yang discloses a memory device, comprising: a plurality of bit lines (BL-1, BL-2, BL-1a, BL-2a) and plurality of word lines WL (see fig. 3); and a plurality of memory cells (12, 12a) (page 41, paragraph 19) at intersections of the plurality of bit lines (BL-1, BL-2, BL-1a, BL-2a) and the plurality of word lines WL (page 3, paragraph 37, see figs. 2 and 3), comprising: a transistor T1 including a source region 28, channel region 26 and drain region 30 in a nanowire structure (page 2, paragraph 27; see fig. 2); and a capacitive device 38 on the transistor T1 (page 2, paragraph 30; see fig. 2) and including a first conductor 42 (inner node; page 2, paragraph 30) in the nanowire structure (see fig. 2).
Regarding Claim 16, Yang discloses wherein the nanowire structure has a diameter less than a width of a word line WL in the plurality of word lines WL (see figs. 2 and 3).
Regarding Claim 17, Yang discloses wherein the nanowire structure has a diameter less than a width of a bit line BL-1 in the plurality of bit lines (BL-1, BL-2, BL-1a, BL-2a) (see figs. 2 and 3).
Regarding Claim 18, Yang discloses wherein the nanostructure extends lengthwise in a first direction (Y-direction in XYZ direction) (see fig. 2), the plurality of word lines WL extend lengthwise in a second direction (X-direction in XYZ direction) perpendicular to the first direction (Y-direction) (see fig. 2), and the plurality of bit lines BL-1, BL-2, BL-1a, BL-2a) extend lengthwise in a third direction (Z-direction in XYZ direction) perpendicular to the first direction (Y-direction) and the second direction (X-direction) (see figs. 2 and 3).
Regarding Claim 19, Yang discloses wherein the transistor T1 further comprises: a gate structure 14 around the channel region 26 (page 2, paragraph 26; see fig. 2) and including a portion of a word line WL of the plurality of word lines WL (page 2, paragraph 24; see fig. 2).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sandhu et al. (US Pub. 2013/0193400; hereinafter “Sandhu”).
Regarding Claim 1, Sandhu discloses a memory cell, comprising: a transistor 48 including a source region 26, channel region 28 and drain region 30 in a nanowire structure (page 2, paragraphs 20 and 30; see fig. 1); and a capacitive device 50 on the transistor 48 (page 2, paragraph 30; see fig. 1) and including a first conductor 38 (page 2, paragraph 24) in the nanowire structure (see fig. 1).
Regarding Claim 7, Sandhu discloses wherein the source region 26, channel region 28 and drain region 30 of the transistor 48 and the first conductor 38 of the capacitive device 50 comprise substantially the same diameter (see figs. 1 and 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ramaswamy (US Pub. 2018/0122817).
Regarding Claim 2, Yang fails to disclose explicitly wherein the nanowire structure comprises a cylindrical structure extending lengthwise in a first direction.
However, Ramaswamy discloses a cylindrical source /drain regions 19 of transistors 16 (page 3, paragraph 40) in a vertical direction (see figs. 4 and 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a cylindrical structure in a transistor, as taught by Ramaswamy, in order to provide uniform gate control around the channel, thereby reducing short channel effects, lowering leakage current, and improving transistor performance.
Regarding Claim 3, Yang discloses wherein the transistor T1 further comprises: a dielectric layer 22 surrounding the channel region 26 (page 2, paragraph 26; see fig. 2); and a gate structure 14 surrounding the dielectric layer 22 (see fig. 2), wherein the gate structure 14 comprises a portion of a word line WL extending lengthwise in a second direction (lateral direction) (page 2, paragraph 24) perpendicular to the first direction (vertical direction) (see fig. 2).
Allowable Subject Matter
Claims 4-6, 8, 13, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 recites a second conductor surrounding the dielectric material opposite the first conductor, wherein the second conductor extends lengthwise in a third direction perpendicular to the first direction and the second direction.
Claim 8 recites the channel region of the transistor comprises a first diameter and the source region and drain region of the transistor comprise a second diameter greater than the first diameter.
Claim 13 recites forming a second conductor of the capacitive device around the dielectric material, wherein the second conductor extends lengthwise in a third direction perpendicular to the first direction and the second direction.
Claim 20 recites a second conductor on a side of the dielectric material opposite the first conductor, and extending lengthwise in the third direction.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 5, 6 and 14 variously depend from claim 4 or 13, so they are objected for the same reason.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 14 of U.S. Patent No. 11,956,940 (hereinafter “Pat-940”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-940 discloses all the claimed limitations. See rejections below.
Regarding Claim 1, Pat-940 discloses a memory cell, comprising: a transistor including a source region, channel region and drain region (see claim 1) in a nanowire structure (see claim 14); and a capacitive device on the transistor and including a first conductor (see claim 1) in the nanowire structure (see claim 14).
Regarding Claim 2, Pat-940 discloses wherein the nanowire structure comprises a cylindrical structure (circular cross-section; see claim 14) extending lengthwise in a first direction (see claim 1).
Claims 1, 2 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 14 and 16 of U.S. Patent No. 11,569,244 (hereinafter “Pat-244”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-244 discloses all the claimed limitations. See rejections below.
Regarding Claim 1, Pat-244 discloses a memory cell, comprising: a transistor including a source region, channel region and drain region in a nanowire structure (forming a nanowire structure; see claim 1); and a capacitive device on the transistor and including a first conductor in the nanowire structure (see claim 1).
Regarding Claim 2, Pat-244 discloses wherein the nanowire structure comprises a cylindrical structure (circular cross section; see claim 14) extending lengthwise in a first direction (see claim 1).
Regarding Claim 10, Pat-244 discloses a method of forming a memory cell, the method comprising: forming a source region, channel region and drain region of a transistor in a nanowire structure (see claim 16); and forming a first conductor of a capacitive device on the source region, channel region and drain region in the nanowire structure (capacitive device vertically over the transistor; see claim 16).
Conclusion
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 July 29, 2026
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