DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-5 in the reply filed on 5/18/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by DOU (US 10014296).
Regarding claim 1, DOU discloses a semiconductor device, including:
a substrate (substrate 302, see fig 20, para 26), having a first region (the regions of the device not between the two gates 370 in fig 20A) and a second region (the region of the device between the two gates 370 in fig 20A), wherein the second region is located between the adjacent first regions;
a fin (the fin 310 comprising 311, 312 and 313, see fig 20, para 27), disposed on the substrate, wherein the fin located in the second region includes a heavily doped region (the heavily doped region 313 to the left of the central gate 370', see fig 20A, para 43);
a gate structure (the left gate 370, see fig 20A, para 48), disposed on the fin and located in the first region (370 is on the fin, and is located outside the region of the device between the two gates 370, see fig 20A);
a single diffusion break (SDB) structure (the central SDB structure 341, see fig 20, para 36), disposed on the fin and located in the second region (the central insulator 341 is located in the region of the device between the two gates 370, see fig 20A); and
a capacitor gate structure (370', which is a gate that forms a capacitor with 313, see fig 20A, para 48), disposed on the fin and located in the second region (370' is located in 20A between the two gates 370),
wherein the capacitor gate structure is disposed on the SDB structure (370' is over 341, see fig 20).
Regarding claim 2, DOU discloses the semiconductor device according to claim 1, wherein the capacitor gate structure partially overlaps the SDB structure (370' and 341 overlap along a vertical line, see fig 20A).
Regarding claim 3, DOU discloses the semiconductor device according to claim 1, wherein a top surface of the SDB structure is lower than a top surface of the fin (the upper surface of 341 is lower than the upper surface of 312, see fig 20A).
Regarding claim 4, DOU discloses the semiconductor device according to claim 1, further including: a dummy source/drain region (the left and right source/drain regions 313 on either side of the gates 370, see fig 20A, para 43), disposed in the fin and located on both sides of the capacitor gate structure (313 are on either side of the central gate 370', see fig 20A).
Regarding claim 5 DOU discloses the semiconductor device according to claim 4, wherein the dummy source/drain region includes an epitaxial layer (313 can be epitaxial layers, see fig 20, para 43).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811