DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 objected to because of the following informalities: the claim appears to have a typographical error, " the image sensors is electrically to at least one". For the purpose of examination, the examiner will interpret the above limitation as " the image sensors is electrically connected to at least one ". Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 2022/0139991.
Re claim 1, Kim teaches an image sensor device (100c fig29, [161]), comprising:
a first semiconductor structure (400, fig31, [161]), comprising:
a first semiconductor substrate (420, fig33, [167]);
logic devices (TR3 and TR3’, fig33, [166]), disposed on the first semiconductor substrate (420, fig33, [167]); and
a through-substrate via (CP5, fig33, [168]), penetrating through the first semiconductor substrate (420, fig33, [167]) and located between two of the logic devices (TR3 and TR3’, fig33, [166]); and
a second semiconductor structure (200, fig31, [160]) bonding with the first semiconductor structure (400, fig31, [161]),
wherein the second semiconductor structure (200, fig31, [160]) comprising:
a second semiconductor substrate (220, fig32, [113]); and
image sensors (221, fig32, [63]), disposed in a pixel area (area under microlenses ML, fig32, [62]) of the second semiconductor substrate,
wherein at least one of the image sensors is electrically connected to at least one of the two of the logic devices (fig29-31).
Re claim 2, Kim teaches the image sensor device of claim 1, wherein the through-substrate via (CP5, fig31 and 33, [168]) is overlapping with the pixel area (area under microlenses ML, fig31 and 32, [62]).
Claim(s) 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. US 2023/0039809.
Re claim 16, Choi teaches an image sensor device (100a, fig4), comprising:
a first semiconductor substrate (320, fig12, [101]) comprising a front side (side of 320 facin330, fig11) and a back side (side of 320 facing 400, fig11) opposite to the front side;
a transistor (TR2, fig11, [101]), disposed on the front side of the first semiconductor substrate;
a first interlayer dielectric layer (340, fig12, [99]), disposed over the front side of the first semiconductor substrate (320, fig12, [99]); a second interlayer dielectric layer (330, fig12, [99]), disposed over the first interlayer dielectric layer (340, fig12, [99]); and
a source/drain contact via (C2_1, fig12, [99]), extending through the first interlayer dielectric layer (340, fig12, [99]) and the second interlayer dielectric layer (330, fig12, [99]), wherein the source/drain contact via (C2_1, fig12, [99]) is electrically connected with the transistor (TR2, fig11, [101]);
a through-substrate via (TSV2, fig12, [123]), extending from the back side of the first semiconductor substrate to beyond the front side of the first semiconductor substrate,
wherein a depth of the through-substrate via (TSV2 in 340, fig12, [123]) beyond the front side of the first semiconductor substrate is less than or equal to a thickness of the first interlayer dielectric layer (340, fig12, [99]).
Re claim 17, Choi teaches the image sensor device of claim 16, further comprises: a second semiconductor substrate (Choi, 200, fig6 and 7, [71]), overlapping with the first semiconductor substrate (Choi, 300, fig7, [99]); and a photodiode (Choi, 221, fig7, [71]), disposed in a pixel area (Choi, area under ML, fig7) of the second semiconductor substrate and electrically connected with the transistor, wherein the through-substrate via is overlapping with the pixel area (Choi, fig7 and 11).
Re claim 18, Choi teaches the image sensor device of claim 16, further comprises: an interlayer conductive layer (Choi, LM, fig14, [123]), located between the first interlayer dielectric layer (Choi, 340, fig12, [99]) and the second interlayer dielectric layer (Choi, 330, fig12, [99]), wherein the through-substrate via (Choi, TSV2, fig12, [123]) is extending into the first interlayer dielectric layer (Choi, 340, fig12, [99]) and in contact with the interlayer conductive layer (Choi, LM, fig14, [123]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-6 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0139991 in view of Choi et al. US 2023/0039809.
Re claim 3, Kim teaches the image sensor device of claim 1, wherein the first semiconductor structure (420, fig33, [167]) further comprises: a gate electrode layer (423, fig33, [166]), comprises a gate electrode (423, fig33, [166]) of the at least one of the two of the logic devices (TR3 and TR3’, fig33, [166]) and a conductive pad (pad directly over CP5/6, fig33); a gate insulation layer (422, fig33, [167]), located between the gate electrode (423, fig33, [166]) and the first semiconductor substrate (420, fig33, [167]) and between the conductive pad (pad directly over CP5/6, fig33) and the first semiconductor substrate (420, fig33, [167]).
Kim does not explicitly show wherein the through-substrate via is penetrating through the gate insulation layer and in contact with the conductive pad.
Choi teaches wherein the first semiconductor structure (300, fig11, [65]) further comprises: a gate electrode layer (323, fig12, [101]), comprises a gate electrode (323, fig12, [101]) and a conductive pad (LM, fig12, [123]); a gate insulation layer (322, fig12, [101]), located between the gate electrode(323, fig12, [101]) and the first semiconductor substrate (320, fig12, [122]) and between the conductive pad (LM, fig12, [123]) and the first semiconductor substrate (320, fig12, [122]), wherein the through-substrate via (TSV2, fig12, [123]) is penetrating through the gate insulation layer (322, fig12, [101]) and in contact with the conductive pad (LM, fig12, [123]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Choi to replace the via structure of Kim with LC-TSV2 of Choi in fig12 between the transistors. The motivation to do so is to form a line with reduced width and pitch to reduce design rule (Choi, [123]).
Re claim 4, Kim does not explicitly show the image sensor device of claim 1, wherein the first semiconductor structure further comprises: an interlayer dielectric structure, disposed over the logic devices; a source/drain contact via, embedded in the interlayer dielectric structure and electrically connected with a source/drain feature of the at least one of the two of the logic devices; a conductive pad, embedded in the interlayer dielectric structure, wherein the through-substrate via is extending into the interlayer dielectric structure and in contact with the conductive pad; and a conductive via, embedded in the interlayer dielectric structure and disposed over the conductive pad, wherein a height of the source/drain contact via is greater than a height of the conductive via.
Choi teaches wherein the first semiconductor structure (300, fig11, [65]) further comprises: an interlayer dielectric structure (330, 340, fig12, [99]), disposed over the logic devices; a source/drain contact via (C2_1, fig12, [99]), embedded in the interlayer dielectric structure (330, 340, fig12, [99]) and electrically connected with a source/drain feature (324, fig12, [101]) of the at least one of the two of the logic devices; a conductive pad (LM, fig12, [123]) embedded in the interlayer dielectric structure, wherein the through-substrate via (TSV2, fig12, [123]) is extending into the interlayer dielectric structure (330, 340, fig12, [99]) and in contact with the conductive pad (LM, fig12, [123]); and a conductive via (LC, fig12, [99]) embedded in the interlayer dielectric structure (330, 340, fig12, [99]) and disposed over the conductive pad (LM, fig12, [123]), wherein a height of the source/drain contact via (C2_1, fig12, [99]) is greater than a height of the conductive via (LC, fig12, [99]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Choi to replace the via structure of Kim with LC-TSV2 of Choi in fig12 between the transistors. The motivation to do so is to form a line with reduced width and pitch to reduce design rule (Choi, [123]).
Re claim 5, Kim modified above teaches the image sensor device of claim 4, wherein the first semiconductor structure (Choi, 300, fig11, [65]) further comprises: an interconnect structure (Choi, ML2, fig12, [123]), disposed over the interlayer dielectric structure (Choi, 330, 340, fig12, [99]) and electrically connected with the conductive via (Choi, LC, fig12, [99]) and the source/drain contact via (Choi, C2_1, fig12, [99]).
Re claim 6, Kim teaches the image sensor device of claim 4, wherein a portion of the interlayer dielectric structure (Choi, 340, fig12, [99]) is disposed between the conductive pad (Choi, LM, fig12, [123]) and the first semiconductor substrate (Choi, 320, fig12, [122]).
Re claim 10, Kim teaches a semiconductor structure (100c fig29, [161]), comprising:
a semiconductor substrate (420, fig33, [167]);
a transistor (TR3 and TR3’, fig33, [166]), disposed on the semiconductor substrate;
an interlayer dielectric structure (430, fig33, [170]), disposed over the transistor;
a source/drain contact via (via over 424, fig33, [167]), embedded in the interlayer dielectric structure and extending from a top surface of the interlayer dielectric structure to a source/drain feature of the transistor (424, fig33, [167]);
Kim does not explicitly show a conductive via, embedded in the interlayer dielectric structure and extending from the top surface of the interlayer dielectric structure into the interlayer dielectric structure, wherein a height of the source/drain contact via is greater than a height of the conductive via; and a through-substrate via, penetrating through the semiconductor substrate and electrically connected with the conductive via.
Choi teaches a conductive via (LC, fig12, [99]), embedded in the interlayer dielectric structure (330, 340, fig12, [99]) and extending from the top surface of the interlayer dielectric structure into the interlayer dielectric structure, wherein a height of the source/drain contact via (C2_1, fig12, [99]) is greater than a height of the conductive via (LC, fig12, [99]); and a through-substrate via (TSV2, fig12, [123]), penetrating through the semiconductor substrate (320, fig12, [99]) and electrically connected with the conductive via (LC, fig12, [99]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Choi to replace the via structure of Kim with LC-TSV2 of Choi in fig12 between the transistors. The motivation to do so is to form a line with reduced width and pitch to reduce design rule (Choi, [123]).
Re claim 11, Kim modified above teaches the semiconductor structure of claim 10, further comprises: a gate electrode layer (Choi, 323 and LM, fig14, [101]) comprising a conductive pad (Choi, LM, fig14, [123]) and a gate electrode of the transistor (Choi, 323, fig14, [101]), wherein the conductive pad (Choi, LM, fig14, [123]) is located between the through-substrate via (Choi, TSV2, fig14, [123]) and the conductive via (Choi, LC, fig14, [99]); and a gate insulation layer (Choi, 322, fig14, [101]), located between the gate electrode (Choi, 323, fig14, [101]) and the semiconductor substrate (Choi, 320, fig14, [99]) and between the conductive pad (Choi, LM, fig14, [123]) and the semiconductor substrate (Choi, 320, fig14, [99]), wherein the through-substrate via (Choi, TSV2, fig14, [123]) is penetrating through the gate insulation layer (Choi, gate insulation layer 322 of transistor on each side of TSV2, fig14).
Re claim 12, Kim does not explicitly show the semiconductor structure of claim 11, wherein a material of the conductive pad comprises polysilicon.
Choi teaches gate electrode formed of polysilicon (323, fig14, [101]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Choi to replace the via structure of Kim with LC-TSV2 of Choi in fig12 between the transistors and form the gate electrode layer and conductive pad in one process with the same material. The motivation to do so is to simplify process step.
Re claim 13, Kim modified above teaches the semiconductor structure of claim 10, wherein the interlayer dielectric structure (Choi, 330, 340, fig12, [99]) comprises: a first interlayer dielectric layer (Choi, 340, fig12, [99]), disposed over the transistor; and a second interlayer dielectric layer (Choi, 330, fig12, [99]), disposed over the first interlayer dielectric layer (Choi, 340, fig12, [99]); and a conductive pad (Choi, LM, fig12, [123]), located between the first interlayer dielectric layer (Choi, 340, fig12, [99]) and the second interlayer dielectric layer (Choi, 330, fig12, [99]) and between the through-substrate via (Choi, TSV2, fig12, [123]) and the conductive via (Choi, LC, fig12, [99]).
Re claim 14, Kim modified above teaches the semiconductor structure of claim 13, wherein the source/drain contact via (Choi, C2_1, fig12, [99]) is penetrating through the first interlayer dielectric layer (Choi, 340, fig12, [99]) and the second interlayer dielectric layer (Choi, 330, fig12, [99]), and the conductive via (Choi, LC, fig12, [99]) is penetrating through the second interlayer dielectric layer (Choi, 330, fig12, [99]).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0139991 in view of Yen et al. US 2011/0193241.
Re claim 7, Kim does not explicitly show the image sensor device of claim 1, wherein the through-substrate via comprises: a conductive plug , embedded in the first semiconductor substrate; a barrier layer, surrounding the conductive plug; a dielectric layer, disposed between the barrier layer and the first semiconductor substrate; and a mask layer, disposed between the dielectric layer and the barrier layer, wherein a portion of the barrier layer is in contact with the dielectric layer, and another portion of the barrier layer is in contact with the mask layer.
Yen teaches wherein the through-substrate via (410-440, fig4H) comprises: a conductive plug (460-440, fig4H, [40, 42, 43]), embedded in the first substrate (406, fig4H, [22]); a barrier layer (426, fig4E, [37]), surrounding the conductive plug (460-440, fig4F and 4H, [40, 42, 43]); a dielectric layer (410, fig4E, [27]), disposed between the barrier layer a (426, fig4E, [37]) and the first substrate (406, fig4H, [22]); and a mask layer (424, fig4E, [31]), disposed between the dielectric layer (410, fig4E, [27]) and the barrier layer (426, fig4E, [37]), wherein a portion of the barrier layer (top part of 426, fig4E, [37]) is in contact with the dielectric layer (410, fig4E, [27]), and another portion of the barrier layer (lower part of 426, fig4E, [37]) is in contact with the mask layer (424, fig4E, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Yen to form the TSV with the process of Yen as in fig4A-4H. The motivation to do so is to improve adhesion between material layer (Yen, [31]), improve electrical characteristics (Yen, [41]) and improve device reliability by releasing stress of each material layer in the hole (Yen, [42]).
Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0139991 in view of Lee et al. US 2014/0084375.
Re claim 8, Kim does not explicitly show the image sensor device of claim 1, wherein the through-substrate via comprises: a first conductive plug, extending from a front side of the first semiconductor substrate into the first semiconductor substrate, wherein the logic devices are disposed on the front side of the first semiconductor substrate; a second conductive plug, extending from a back side of the first semiconductor substrate into the first semiconductor substrate, and electrically connected with the first conductive plug; a first dielectric layer, laterally disposed between the first conductive plug and the first semiconductor substrate; and a second dielectric layer, laterally disposed between the second conductive plug and the first semiconductor substrate.
Lee teaches wherein the through-substrate via comprises: a first conductive plug (240, fig1C, [47]), extending from a front side (FS, fig1C) of the first semiconductor substrate into the first semiconductor substrate (100, fig1C, [41]), wherein the logic devices (110, fig1C, [42]) are disposed on the front side of the first semiconductor substrate; a second conductive plug (440, fig1D, [59]), extending from a back side of the first semiconductor substrate (BS, fig1C) into the first semiconductor substrate, and electrically connected with the first conductive plug (240, fig1C, [47]); a first dielectric layer (210, fig1D, [48]), laterally disposed between the first conductive plug (240, fig1C, [47]) and the first semiconductor substrate (100, fig1C, [41]); and a second dielectric layer (325, fig1D, [55]), laterally disposed between the second conductive plug (440, fig1D, [59]) and the first semiconductor substrate (100, fig1C, [41]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Lee to form the TSV with the process of Lee. The motivation to do so is to protect back side BE of TSV from etch process and improve yield, performance, and life cycle (Lee, [63]).
Re claim 9, Kim modified above teaches the image sensor device of claim 8, wherein the through-substrate via (Lee, 400, 200, fig1D) comprises: a first barrier layer (Lee, 220, fig1C, [47]), laterally disposed between the first conductive plug (Lee, 240, fig1C, [47]) and the first dielectric layer (Lee, 210, fig1D, [48]), wherein the second dielectric layer (Lee, 325, fig1D, [55]) is in contact with the first barrier layer (Lee, 220, fig1D, [47]); and a second barrier layer (Lee, 420, fig1D, [59]), laterally disposed between the second conductive plug (Lee, 440, fig1D, [59]) and the second dielectric layer (Lee, 325, fig1D, [55]), wherein the second barrier layer (Lee, 420, fig1D, [59]) is in contact with the first barrier layer (Lee, 210, fig1D, [48]).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. US 2023/0039809 in view of Yen et al. US 2011/0193241.
Re claim 20, Choi does not explicitly show the image sensor device of claim 16, wherein the through-substrate via comprises: a first conductive plug, extending from a top surface of the first interlayer dielectric layer into the first semiconductor substrate; and a second conductive plug, extending from the back side of the first semiconductor substrate into the first semiconductor substrate, and electrically connected with the first conductive plug.
Yen teaches wherein the through-substrate via (410-440, fig4H) comprises: a first conductive plug (460, fig4H, [38]), extending from a top surface of the first interlayer dielectric layer (surface of 404 in contact with 400, fig4H, [22]) into the first substrate (406, fig4H, [22]); and a second conductive plug (440, fig4H, [43]), extending from the back side (406a, fig4H, [21]) of the first semiconductor substrate into the first substrate (406, fig4H, [22]), and electrically connected with the first conductive plug (460, fig4H, [38]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Choi and Yen to form the TSV with the process of Yen as in fig4A-4H. The motivation to do so is to improve adhesion between material layer (Yen, [31]), improve electrical characteristics (Yen, [41]) and improve device reliability by releasing stress of each material layer in the hole (Yen, [42]).
Allowable Subject Matter
Claim 15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to reduce depth and size of TSV and provide greater design flexibility.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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