DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 13-32 in the reply filed on 06/05/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mittal(USPGPUB DOCUMENT: 2016/0334845, hereinafter Mittal) in view of Ibaraki (USPGPUB DOCUMENT: 2010/0219525, hereinafter Ibaraki).
Re claim 13 Mittal discloses in Fig 21 a method of manufacturing an integrated circuit (IC) device, the method comprising: forming a substrate(240/220); forming a first connection layer(228/252), depositing a dielectric layer(246/224) over the first connection layer(228/252); patterning first holes in the dielectric layer(246/224); patterning second holes in the dielectric layer(246/224); wherein the first connection layer(228/252) comprises first wires; wherein the second connection layer comprises second wires;
Mittal does not discloses forming a metallization layer over a first side of a substrate(240/220); forming a first connection layer(228/252) over the metallization layer, patterning first holes in the dielectric layer(246/224); filling the first holes with a first semiconductor having P-type doping so as to form P-type vias; patterning second holes in the dielectric layer(246/224); filling the second holes with a second semiconductor having N-type doping so as to form N-type vias; conducting planarization, wherein planarization provides a planarized surface and the planarized surface comprises the dielectric layer(246/224), the P-type vias, and the N-type vias; and forming a second connection layer over the planarized surface, wherein the first wires form first connections between the P-type vias and the N- type vias; andthe second wires form second connections between the P-type vias and the N-type vias.
Ibaraki discloses in Fig 3 discloses forming a metallization layer(left/right 134/150), patterning first holes[0037]; filling the first holes with a first semiconductor having P-type doping so as to form P-type vias[0041]; patterning second holes[0037]; filling the second holes with a second semiconductor having N-type doping so as to form N-type vias[0041];
Ibaraki discloses in Fig 3 wherein the first metal interconnect structure(2127/2120) comprises a plurality of metallization layers(left/right 134/150) and a passivation stack(106/108/144) over the plurality of metallization layers; and the thermoelectric cooler(Peltier element/112N/112P)[0008] is configured to transfer heat[0025] from the semiconductor substrate(substrate(240/220) of 104/116).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Ibaraki to the teachings of Mittal in order to provide a semiconductor device having improved heat dissipation efficiency [0007, Ibaraki]. In doing so, forming a metallization layer(left/right 134/150) over a first side of a substrate(240/220 of Mittal); forming a first connection layer(228/252 of Mittal) over the metallization layer (left/right 134/150), patterning first holes[0037] in the dielectric layer(246/224 of Mittal); conducting planarization, wherein planarization provides a planarized surface and the planarized surface comprises the dielectric layer(246/224 of Mittal), the P-type vias, and the N-type vias[0041 of Ibaraki]; and forming a second connection layer over the planarized surface, wherein the first wires form first connections between the P-type vias and the N- type vias[0041 of Ibaraki]; patterning second holes[0037 of Ibaraki] in the dielectric layer(246/224 of Mittal); andthe second wires form second connections between the P-type vias and the N-type vias[0041 of Ibaraki].
A CMP or a planarization process for a material removal process would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. KSR, see MPEP 2143.
Re claim 14 Mittal and Ibaraki disclose the method of claim 13, further comprising forming a layer of high thermal conductivity dielectric(712/714) over the second connection layer.
Re claim 15 Mittal and Ibaraki disclose the method of claim 13, further wherein the second connection layer comprises a high thermal conductivity dielectric(712/714).
Re claim 16 Mittal and Ibaraki disclose the method of claim 13, further comprising forming a passivation stack(2124) and a pad layer over the metallization layer, wherein the dielectric layer(246/224) is formed over the pad layer.
Re claim 17 Mittal and Ibaraki disclose the method of claim 16, further comprising: etching holes that extend through the dielectric layer(246/224); and placing solder bumps in the holes.
Re claim 18 Mittal and Ibaraki disclose the method of claim 13, further comprising: forming a semiconductor device on a second side of the substrate(240/220), wherein the substrate(240/220) is a semiconductor substrate(semiconductor substrate of 2142/2143), and the second side is opposite the first side; forming a metal interconnect structure on the second side; bonding the semiconductor substrate(semiconductor substrate of 2142/2143) to a carrier substrate(240/220) through the metal interconnect structure; and thinning the semiconductor substrate(semiconductor substrate of 2142/2143) from the first side prior to forming the metallization layer on the first side.
Re claim 19 Mittal and Ibaraki disclose the method of claim 18, further comprising: forming a buried rail in the second side; coupling the semiconductor device to the buried rail; and forming a through substrate(240/220) via through which power may be provided to the buried rail.
Re claim 20 Mittal and Ibaraki disclose the method of claim 13, wherein the substrate(240/220) is a wafer.
Re claim 21 Mittal discloses in Fig 21 a method of manufacturing an integrated circuit (IC) device, the method comprising: forming a first metal interconnect structure(2127/2120) on a first side of a semiconductor substrate(semiconductor substrate of 2142/2143), forming a thermoelectric cooler(2110/2150) at least partially within the passivation stack(2124); and coupling the semiconductor substrate(semiconductor substrate of 2142/2143) to a dielectric substrate(240/220/250/226) such that the thermoelectric cooler(2110/2150) is between the semiconductor substrate(semiconductor substrate of 2142/2143) and the dielectric substrate(240/220/250/226)
Mittal does not discloses wherein the first metal interconnect structure comprises a plurality of metallization layers and a passivation stack(2124) over the plurality of metallization layers; and the thermoelectric cooler is configured to transfer heat from the semiconductor substrate (semiconductor substrate of 2142/2143) toward the dielectric substrate(240/220/250/226).
Ibaraki discloses in Fig 3 wherein the first metal interconnect structure(2127/2120) comprises a plurality of metallization layers(left/right 134/150) and a passivation stack(106/108/144) over the plurality of metallization layers; and the thermoelectric cooler(Peltier element/112N/112P)[0008] is configured to transfer heat[0025] from the semiconductor substrate(substrate(240/220) of 104/116).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Ibaraki to the teachings of Mittal in order to provide a semiconductor device having improved heat dissipation efficiency [0007, Ibaraki]. In doing so, the thermoelectric cooler(Peltier element/112N/112P)[0008] is configured to transfer heat[0025] from the semiconductor substrate(substrate(240/220) of 104/116) toward the dielectric substrate(240/220)(250/226 of Mittal).
Re claim 22 Mittal and Ibaraki disclose the method of claim 21, wherein forming the thermoelectric cooler(2110/2150) comprises forming first vias of N-type semiconductor and second vias of P-type semiconductor in the passivation stack(2124).
Re claim 23 Mittal and Ibaraki disclose the method of claim 22, further comprising: forming a second metal interconnect structure on a second side of the semiconductor substrate(semiconductor substrate of 2142/2143) opposite the first side; forming a semiconductor device on the second side; and forming a through substrate(240/220) via through the semiconductor substrate(semiconductor substrate of 2142/2143) to couple a power rail in the first metal interconnect structure(2127/2120) to the semiconductor device.
Re claim 24 Mittal and Ibaraki disclose the method of claim 21, where the passivation stack(2124) comprises a layer of an extremely high thermal conductivity dielectric.
Re claim 25 Mittal and Ibaraki disclose the method of claim 21, further comprising attaching a lid over a side of the semiconductor substrate(semiconductor substrate of 2142/2143) opposite the dielectric substrate(240/220/250/226).
Re claim 26 Mittal discloses in Fig 21 a method of manufacturing an integrated circuit (IC) device, the method comprising: forming solder connections(252/230/232/234/236) over a first side of a first substrate(240/220); and forming a thermoelectric cooler(2110/2150) in a layer with the solder connections(252/230/232/234/236) such that the thermoelectric cooler(2110/2150) is lateral to the solder connections(252/230/232/234/236)
Mittal does not discloses the thermoelectric cooler(210) is configured to pump heat away the first substrate(240/220).
Ibaraki discloses in Fig 3 the thermoelectric cooler(Peltier element/112N/112P)[0008] is configured to pump heat away[0025] the first substrate(240/220)(substrate(240/220) of 104/116).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Ibaraki to the teachings of Mittal in order to provide a semiconductor device having improved heat dissipation efficiency [0007, Ibaraki].
Re claim 27 Mittal and Ibaraki disclose the method of claim 26, wherein forming the thermoelectric cooler(2110/2150) comprises forming a high thermal conductivity dielectric layer(246/224).
Re claim 28 Mittal and Ibaraki disclose the method of claim 26, wherein forming the thermoelectric cooler(2110/2150) comprises forming an extremely high thermal conductivity dielectric layer(246/224).
Re claim 29 Mittal and Ibaraki disclose the method of claim 26, wherein forming the solder connections(252/230/232/234/236) comprises placing first and second solder bumps such that the thermoelectric cooler(2110/2150) is between the first and second solder bumps.
Re claim 30 Mittal and Ibaraki disclose the method of claim 26, further comprising: forming a first metal interconnect structure(2127/2120) on the first side and a second metal interconnect structure on a second side of the first substrate(240/220) opposite the first side; forming a semiconductor device on the second side; and forming a through substrate(240/220) via through the first substrate(240/220) to provide power from the first metal interconnect structure(2127/2120) to the semiconductor device.
Re claim 31 Mittal and Ibaraki disclose the method of claim 26, further comprising bonding the first substrate(240/220) to a printed circuit board through the solder connections(252/230/232/234/236).
Re claim 32 Mittal and Ibaraki disclose the method of claim 31, wherein the solder connections(252/230/232/234/236) comprise a ball grid array.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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