DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group II in the reply filed on July 15, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 6, 2024; and February 5, 2026 were considered by the examiner. The amount of consideration given to the Taiwanese office actions on the IDS filed February 5, 2026 is de minims as they are not in English, nor was a machine translation provided.
Drawing Objections
The drawings are objected to because:
In figure 2B, element 212 is not discussed in the specification.
In figure 4E, element 414 is not discussed in the specification.
In figure 4F, the element surrounding Gate is unlabeled, the hashed line above 406 is unlabeled, the white box above the hashed line above 406 is unlabeled. Applicant needs to label these boxes or remove them.
In figures 5A-5D there is are two boxes above 502 and on the left and right of 504 which are unlabeled. Applicant needs to label these boxes or remove them.
The claimed subject matter of claim 28 must be shown, or the features of the claim must be canceled. Applicant has not drawings showing a stack of alternating insulating and gate electrodes.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 28 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 28,
Applicant does not have support for the limitation of claim 28. There is no figure directed to claim 28, and Examiner cannot find where Applicant has possession of a written description such that it would enable one of ordinary skill in the art to make the device with alternating insulating layers and gate electrodes. The specification and originally filed disclosure appears to be silent with respect to this limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12, 19, and 21-25 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Yeh et al. (US 2018/0151751 A1) (“Yeh”).
Regarding claim 12, Yeh teaches at least in figures 2A-2H:
forming a layer of a two-dimensional (2D) material (204);
forming a layer of an insulating material (214) on the 2D material (204);
etching away a portion of the insulating material to form a feature and expose a surface of the 2D material (Figure 2G and ¶ 0026); and
filling the feature with a metal (230),
wherein the metal contacts (230) the surface of the 2D material (204).
Regarding claim 19, Yeh teaches at least in figures 2A-2H:
wherein the semiconductor device comprises a planar device, the feature comprises a vertical hole with the 2D material exposed at a bottom of the vertical hole, and the metal fills the vertical hole to form an electrode of the semiconductor device (this is shown at least in figure 2G).
Regarding claim 21,
Claim 21 is rejected for the same reasons as claim 12 above.
Regarding claim 22, Yeh teaches at least in figures 2A-2H:
wherein the metal (230) comprises a protective metal liner directly contacting the 2D material and a bulk metal fill material (¶ 0027, where one or more materials listed can be used and can be formed by PVD. This would created a plurality of layers of different material for example Ti or TiN followed by Cu, or any other combination of layers/combinations can be used), and
wherein the protective metal liner comprises at least one of nickel (Ni), titanium (Ti), or titanium nitride (TiN) (¶ 0027, where if one uses a combination of materials they could treat the first material that goes down as the protective metal liner and the material that goes on top as the bulk metal fill material. For example using PVD one could first form a TiN layer, and the using PVD form a Cu layer. Thereby using a combination of the listed materials).
Regarding claim 23-24, Yeh teaches at least in figures 2A-2H:
herein the 2D material comprises a MoS2 monolayer or bilayer (¶¶ 0014 and 17, where MoS2 can be used and can be formed as a monolayer).
Regarding claim 25, Yeh teaches at least in figures 2A-2H:
wherein the channel layer (204) is formed as a planar channel layer (see figure 2G), and
wherein filling the feature with the metal forms a drain or a source for the semiconductor device (see figure 2G).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, in view of Lin et al. (US 2017/0222005 A1) (“Lin”), in view of Grant et al. (US 5,439,553) (“Grant”).
Regarding claim 13, Yeh does not explicitly teach:
wherein etching away the portion of the insulating material comprises performing a plasma-free vapor etch.
Rather, Yeh teaches:
Atomic layer etch (“ALE”).
Lin teaches:
Dry etching, wet etching, ALE, etc are all art recognized equivalents for the same purpose of etching a silicon oxide (SiO2) layer. ¶¶ 0028-29. Therefore, these etching techniques are considered obvious variants of each other.
Grant teaches at least in figures 3-6:
wherein etching away the portion of the insulating material comprises performing a plasma-free vapor etch (col. 2-3 at lines 50-15, where etching is performed without plasma and uses vapors).
It would have been obvious to one of ordinary skill in the art to use the etching technique of Grant because it prevents it prevents the condensation of reactants and other contaminations which may affect the resulting surface after etching. Col. 3 at lines 35-45.
Regarding claim 14, Grant teaches at least in figures 3-6:
wherein etching away the portion of the insulating material comprises maintaining a temperature of less than or about 45 C (Grant teaches that etch rate is a result effective variable based upon at least temperature and pressure; see figure 2 where one can etch with the temperature less than 45 C) such that 2D material is free of oxidation (as stated in claim 13 above, this purpose of Grant’s method is to reduce contamination (oxidation) on the surface after etch).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, in view of Lin, in view of Grant, in view of Tien et al. (US 10,937,652 B1) (“Tien”).
Regarding claim 15, Grant teaches at least in figures 3-6:
wherein etching away the portion of the insulating material comprises providing an HF etch gas with an carrier gas with a flow rate ratio of approximately 1:1 (col. 6 at lines 14-24, where the flow rate ratio can be 0-6.).
Grant does not teach:
The carrier gas is NH3.
Grant teaches the carrier gas is CH3OH.
Tien teaches:
That CH3OH and NH3 (col. 4 at lines 53-56) are art reconzied equivalent carrier gases used with an HF etchant. MPEP 2144.06-07.
Regarding claim 16, Grant teaches at least in figures 3-6:
That one can increase the wafer temperature to 110 C. This result effective variable allows one to change the etch rate of the wafer as shown in figure 2. Examiner notes here that the claim states the etching process (i.e. etching away) happens as part of the etching process. This means that the anneal can be considered raising the temperature of the etch. Grant teaches this will increase the etch rate.
In regards to moving the semiconductor device closer to the top plate this would have been obvious to one of ordinary skill in the art. It would have been obvious because there are limited options to heat the wafer. These limited options are heating the wafer from the bottom, top, or around. An everyday example of this is an oven in ones house. One can heat the food from the bottom, one can beat the food but use convection to move the heat around, or one can heat the food using the broiler (i.e. top heat). Therefore, it would have been obvious to one of ordinary skill in the art that if they were using a top heat device that they could move the wafer closer to the heat in order to increase the temperature of the wafer and thereby increasing the etch rate. This would have been obvious to try based upon the etching equipment one used.
wherein etching away the portion of the insulating material comprises increasing a temperature of the semiconductor device by moving the semiconductor device closer to a top plate of a processing chamber and performing an anneal of between about 1100 C and about 1300 C.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, in view of Applicant (US 2020/0335331 A1) (“Applicant”), in view of Applicant II (US 2004/0077161 A1) (“Applicant II”).
Regarding claims 17-18, Yeh teaches:
That PVD can be used to form the metal fill. ¶ 0027.
Yeh does not teach:
The particulars of the PVD process.
Applicant teaches:
That the target can be tilted (figure 7) or the semiconductor device (figure 8) can be tilted in PVD process. Applicant taught that by changing the tilt angle one is able to improve film uniformity. ¶ 0084
The controller of the PVD device can be used to control any of the processes described including the power and gas pressure. ¶ 0082.
Applicant II teaches:
That one would want the pressure of the chamber during a PVD process to be about 0.1 mtorr (0.0001 torr) to about 100 torr, and have a power (bias power) be 1 watt to 500 watt).
It would have been obvious to one of ordinary skill it the art to combine Applicant’s own work with Yeh as Yeh is silent with respect to the particulars of the PVD process, and Applicant is well-known a semiconductor equipment manufacturer who sells PVD devices. Thus, it would have been obvious that their own work would be able to help one of ordinary skill in the art determine the necessary particulars for using a PVD process.
Claim(s) 20, and 27-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, in view of Chen et al. (US 2004/0077161 A1).
Regarding claim 20, Yeh teaches at least in figures 2A-2H:
A planar transistor.
Yeh does not teach:
wherein the semiconductor device comprises
a three-dimensional (3D) NAND memory device,
the feature comprises a vertical channel hole that is conformally lined with the 2D material, and
the metal substantially fills the vertical channel hole inside of the 2D material.
Chen teaches at least in figure 4A:
wherein the semiconductor device comprises
a three-dimensional (3D) NAND memory device (¶ 0053),
the feature comprises a vertical channel hole (where 420 is) that is conformally lined with the 2D material (420) , and
the metal (412) substantially fills the vertical channel hole inside of the 2D material (420).
Examiner takes official notice that semiconductor devices can be planar, or flat, or can be vertical. These are well-known orientations of semiconductors devices, and it is obvious that based upon space constraints and power requirements for the resulting device, along with functional requirements (i.e. logic or memory) that one could freely choose which orientation they want to make the semiconductor device in.
Regarding claim 27,
Claim 27 is obvious for the reasons as claim 20 above.
Regarding claim 28,
Claim 28 is how a NAND device is formed. Examiner is taking official notice of this.
Regarding claims 29-31,
Claims 29-31 are rejected for the same reasons as claim 20 above and shown in at least figure 4A of Chen.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh.
Regarding claim 26, Yeh does not teach:
wherein a vertical side of the channel layer is free of contact with the metal.
Yeh teaches one wants to have the vertical side of the channel layer to touch the metal in order to gain the benefit of reducing contact resistance.
However, if one does not want this benefit then it would have been obvious to one of ordinary skill in the art to not have the metal contact the vertical side of the channel layer. MPEP 2144.04(II). One may which to do this in order to form Schottky contacts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST.
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/VINCENT WALL/Primary Examiner, Art Unit 2898
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