DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group II in the reply filed on July 13, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 25, 2024; and May 29, 2025 were considered by the examiner.
Drawing Objections
The numerous figures have not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the figures.
The drawings are objected to because:
Figures 6D and 6E needs to add “top down” to said figures. It is unclear from the drawings which view one is seeing. Applicant needs to do this for all top down views.
The claimed subject matter of claim 8 “doping exposed portions of the dummy gate dielectric layer with first dopants”. Is not shown in the drawings. Applicant must show this claimed subject matter.
The claimed subject matter of claim 16 needs to be shown for the same reason as objection 2 above.
The claimed subject matter of claim 24 needs to be shown for the same reasons as objection 2 above. Further, none of the claimed method steps in figure 24 are shown.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification Objections
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In ¶ 0034, Applicant needs to add “(not shown)” after the sentence “In some embodiments, the portions of the dummy gate dielectrics 71 (e.g., the portions adjacent the exposed tilted sidewalls) may be removed by a doping process and an etching process.”
In ¶ 0034, Applicant needs to add “(not shown)” after the sentence “The exposed portions of the dummy gate dielectrics 71 may be doped by a suitable doping process, such as implantation doping or the like.”
In ¶ 0034, Applicant needs to add “(not shown)” after the sentence “During the doping process, the STI regions 68A (circled in Figure 7B by dotted lines) may also be doped.”
In ¶ 0034, Applicant needs to add “(not shown)” after the sentence “The STI regions 68A may be upper portions of the STI regions 68 adjacent the exposed top surfaces of the STI regions 68A.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-24, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0351976 A1) (“Lee”).
Regarding claim 21, Lee teaches:
forming a first semiconductor nanostructure (55) over a semiconductor fin (66);
forming an isolation region (68) on a sidewall of the semiconductor fin (66);
forming a dummy gate dielectric layer (70) on the first semiconductor nanostructure (55),
wherein a first portion of the dummy gate dielectric layer has a shape of a trapezoid in a top-down view (This is not shown in the figures for the manufacture of the device of Lee. However, as Lee is using the same process as claimed and described in the current applications specification it would have been obvious that one of ordinary skill in the art following the directions of Lee would obviously meet this limitation. It would appear that in the current application Applicant is giving more detail of the process than they disclosed in the Lee reference. However, there is no evidence that this shape as shown in Applicant’s figure 6D is anything other than expected when forming the device);
forming a dummy gate layer (76) on the dummy gate dielectric layer (70),
wherein the first portion of the dummy gate dielectric layer comprises a first side in contact with a first sidewall of the first semiconductor nanostructure and a second side in contact with a first portion of the dummy gate layer (70 is sandwiched between 76 and 55), and
wherein the first side of the first portion of the dummy gate dielectric layer is longer than the second side of the first portion of the dummy gate dielectric layer in the top-down view (this view is not shown in Lee however, this appears to also be directed to figure 6D, and would be obvious for the same reasons as discussed in the trapezoid shape above); and
partially removing the first portion of the dummy gate dielectric layer (This is shown in figure 6B, where 70 has been partially removed to form 71),
wherein the first portion of the dummy gate dielectric layer has a shape of a rectangle in the top-down view after partially removing the first portion of the dummy gate dielectric layer (This is not shown in the figures of Lee, but since Lee performs the same claimed process and disclosed the same, or substantially similar, process as Applicant the etching of the dummy gate shown in figure 6B would have obviously formed the claimed shape.).
Regarding claims 22-23,
Claims 22-23 are further directed to the top view after etching the dummy gate dielectric layer. As stated in claim 21, because the prior art teaches the same etching process of the dummy gate dielectric layer it is obvious that it will have the resulting dummy gate dielectric shape after etching it.
Regarding claim 24, Lee teaches:
wherein partially removing the first portion of the dummy gate dielectric layer comprises (detailed below):
performing an implantation process to partially dope the dummy gate dielectric layer with a first dopant (¶ 0036; figures 7A-7B); and
performing an etching process to remove doped portions of the dummy gate dielectric layer (¶ 0037, figures 8A-8B).
Regarding claim 27, Lee teaches:
wherein the implantation process dopes a top portion of the isolation region with the first dopant (It would have been obvious to one of ordinary skill in the art that some of the implantation process of Lee would, or could, have doped a top portion of 68. This would have come down to whether one want to use a mask or not to block the dopants from entering 68. According to Lee the use of a mask is optional as it uses the term “may”, and not “must” when discussing the mask in ¶ 0036. Therefore, if one chooses not to use as mask as not using it would save process steps, thereby time, thereby money, then the doping discussed in ¶ 0036 would obviously dope the isolation region 68).
Claim(s) 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Kim et al. (US 2018/0130886 A1) (“Kim”).
Regarding claim 25-26, Lee teaches:
The dopant is a n-type impurity or p-type impurity. ¶ 0036. Lee does not teach,
What the impurity is.
Kim teaches:
A similar device to Lee. Kim teaches that an n-type impurity is nitrogen, ¶ 0086, and p-type impurity can comprise fluorine, ¶ 0085.
Therefore, Kim teaches the limitations of claims 25-26.
It would have been obvious for one of ordinary skill in the art to combine Kim with Lee as Lee does not teach the impurity. Therefore, one would have been motivated to find a reference which teaches this.
Allowable Subject Matter
Claims 8-20 are allowed.
The following is an examiner’s statement of reasons for allowance: see below.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Regarding claim 8, Lee teaches:
forming a stack of nanostructures (55) over a fin (66),
wherein the stack of nanostructures (55) comprises (detailed below)
a first nanostructure (at least one of the nanostructures shown in figure 3);
forming a dummy gate structure (70/72/76) over the stack of nanostructures (55),
the dummy gate structure (70/72) comprising (detailed below)
a dummy gate dielectric layer (70) on a top surface and sidewalls of the stack of nanostructures (55) (shown in figure 5) and a dummy gate layer (72/76) over the dummy gate dielectric layer (55),
wherein the dummy gate dielectric layer has a first width at an interface between the dummy gate dielectric layer and a first sidewall of the first nanostructure in a top-down view (This is not shown in the figures for the manufacture of the device of Lee. However, as Lee is using the same process as claimed and described in the current applications specification it would have been obvious that one of ordinary skill in the art following the directions of Lee would obviously meet this limitation. It would appear that in the current application Applicant is giving more detail of the process than they disclosed in the Lee reference. However, there is no evidence that this first width as shown in Applicant’s figure 6D is anything other than expected when forming the device);
etching the exposed portions of the dummy gate dielectric layer (¶ 0034 and figure 6B),
Regarding the limitation,
wherein after etching the exposed portions of the dummy gate dielectric layer,
the dummy gate dielectric layer has a second width at the interface between the dummy gate dielectric layer and the first sidewall of the first nanostructure in the top-down view, and
wherein the second width is smaller than the first width
This is not shown in the figures of Lee. However, as was stated above for a previous limitation, because the prior art is following the same steps, and making a substantially similar device it would have been obvious that the device of Lee would meet this limitation.
Lee does not expressly teach:
doping exposed portions of the dummy gate dielectric layer with first dopants.
Regarding claim 16,
Claim 16 is allowable for the same reasons as claim 20 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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