DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-21, 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawada(USPGPUB DOCUMENT: 2021/0167167, hereinafter Kawada) in view of Sakai (USPGPUB DOCUMENT: 2021/0074816, hereinafter Sakai) and Harrington (USPGPUB DOCUMENT: 2022/0130997, hereinafter Harrington).
Re claim 1 Kawada discloses a semiconductor device, comprising: a substrate(40) that has a first conductivity type(n-type)[0160]; an epitaxial layer(43/42) on the substrate(40), wherein the epitaxial layer(43/42) has the first conductivity type(n-type)[0160]; a first device, comprising: a first trench gate structure(left 7/right 7) that extends downward from a top surface of the epitaxial layer(43/42) into the epitaxial layer(43/42), wherein the substrate(40) functions as a drain region[0089] of the first device; and a first shielding portion(11a/11) that is positioned below the first trench gate structure(left 7/right 7) and in contact with a bottom portion of the first trench gate structure(left 7/right 7), wherein the first shielding portion(11a/11) has a second conductivity type(p-type)[0078]; and a second device that is separated from the first device and electrically connected to the first device, wherein the second device comprises: a second trench gate structure(left 7/right 7) that extends downward from the top surface of the epitaxial layer(43/42) into the epitaxial layer(43/42); and a second shielding portion(11a/11) that is positioned under the second trench gate structure(left 7/right 7) and in contact with a bottom portion of the second trench gate structure(left 7/right 7), wherein the second shielding portion(11a/11) has the second conductivity type(p-type)[0078].
Kawada does not discloses a planar gate structure that is formed over the top surface of the epitaxial layer; wherein the first trench gate structure and the second trench gate structure are split-trench gate structures, and each of the split-trench gate structures comprises a bottom conductive portion and an insulating layer that covers sidewalls of the bottom conductive portion, andwherein the bottom conductive portion of the first trench gate structure is at least partially in direct contact with the first shielding portion, and the bottom conductive portion of the second trench gate structure is at least partially in direct contact with the second shielding portion.
Sakai discloses a planar gate structure(GE) that is formed over the top surface of the epitaxial layer(EP1/EP2);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sakai to the teachings of Kawada in order to enhance the reliability of semiconductor device [0006, Sakai].
Kawada and Sakai does not discloses wherein the first trench gate structure and the second trench gate structure are split-trench gate structures, and each of the split-trench gate structures comprises a bottom conductive portion and an insulating layer that covers sidewalls of the bottom conductive portion, andwherein the bottom conductive portion of the first trench gate structure is at least partially in direct contact with the first shielding portion, and the bottom conductive portion of the second trench gate structure is at least partially in direct contact with the second shielding portion.
Harrington discloses in Fig 11 wherein the first trench gate structure(left/right 686)[0205] and the second trench gate structure(left/right 686)[0205] are split-trench gate structures, and each of the split-trench gate structures comprises a bottom conductive portion and an insulating layer(663/662) that covers sidewalls of the bottom conductive portion, andwherein the bottom conductive portion of the first trench gate structure is at least partially in direct contact with the first shielding portion(left/right 670), and the bottom conductive portion of the second trench gate structure is at least partially in direct contact with the second shielding portion(left/right 670).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Harrington to the teachings of Kawada in order to provide enhanced performance [0007, Harrington].
Re claim 2 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 1, each of the split-trench gate structure(left 7/right 7)s further comprises: a top conductive portion over the bottom conductive portion; and wherein the insulating layer further covers sidewalls of the top conductive portion, wherein the insulating layer extends between the bottom conductive portion and the top conductive portion to electrically isolate the bottom conductive portion from the top conductive portion.
Re claim 4 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 1, wherein the first trench gate structure(left 7/right 7) and the second trench gate structure(left 7/right 7) have the same vertical depth in the epitaxial layer(43/42).
Re claim 5 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 1, wherein the first shielding portion(11a/11) and the second shielding portion(11a/11) are positioned at the same horizontal level.
Re claim 6 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 1, wherein the first trench gate structure(left 7/right 7) and the second trench gate structure(left 7/right 7) extend in a first direction, and the first device and the second device are separated from each other in a second direction, wherein the second direction is different from the first direction, and the second device further comprises: a source region and a drain region[0089] that correspond to opposite sides of the planar gate structure, wherein the source region and the drain region[0089] are separated from each other in the first direction.
Re claim 7 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 6, wherein the second device includes two second trench gate structure(left 7/right 7)s that are separated from each other in the second direction, wherein the planar gate structure, the source region and the drain region[0089] are positioned between the two second trench gate structure(left 7/right 7)s, and wherein one set of opposite sidewalls of the planar gate structure extends in the first direction, and the other set of opposite sidewalls of the planar gate structure corresponds to the source region and the drain region[0089] and extends between the two second trench gate structure(left 7/right 7)s.
Re claim 8 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 1, wherein the first device further comprises: a current spreading layer that is formed in the epitaxial layer(43/42) and in contact with the first shielding portion(11a/11), wherein the current spreading layer has the first conductivity type(n-type)[0160], and a doping concentration of the current spreading layer is greater than a doping concentration of the epitaxial layer(43/42); a body region that is formed in the current spreading layer and extends downward from the top surface of the epitaxial layer(43/42), wherein the body region has the second conductivity type(p-type)[0078]; and a first heavily doped portion that is formed in the body region and extends downward from the top surface of the epitaxial layer(43/42), wherein the first heavily doped portion has the first conductivity type(n-type)[0160] and acts as a source region of the first device.
Re claim 9 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 8, wherein the first device includes two first trench gate structure(left 7/right 7)s that are separated from each other in the second direction and two first shielding portion(11a/11)s that are under the two first trench gate structure(left 7/right 7)s, wherein the current spreading layer extends between the two first trench gate structure(left 7/right 7)s, and a bottom surface of the current spreading layer is coplanar with bottom surfaces of the two first shielding portion(11a/11)s.
Re claim 10 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 1, wherein the second device further includes: a well region that extends downward from the top surface of the epitaxial layer(43/42) to contact the second shielding portion(11a/11), a sidewall of the well region is in contact with the second trench gate structure(left 7/right 7), and the well region has the second conductivity type(p-type)[0078], wherein the planar gate structure is positioned above the well region; and first heavily doped portions that are formed in the well region and extend downward from the top surface of the epitaxial layer(43/42), wherein the first heavily doped portions have the first conductivity type(n-type)[0160] and act as a source region and a drain region[0089] of the second device.
Re claim 11 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 1, further comprising: a third device that is separated from the first device, wherein the third device is electrically connected to the second device, and the third device comprises: a third trench gate structure(left 7/right 7) that extends downward from the top surface of the epitaxial layer(43/42) into the epitaxial layer(43/42).
Re claim 12 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 11, wherein the second shielding portion(11a/11) that is under the second trench gate structure(left 7/right 7) extends continuously to a position that is under the third trench gate structure(left 7/right 7), and the second shielding portion(11a/11) is in direct contact with the third trench gate structure(left 7/right 7), wherein the second shielding portion(11a/11) is electrically connected to the third trench gate structure(left 7/right 7).
Re claim 13 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 12, wherein the third device further comprises: a current spreading layer that is formed in the epitaxial layer(43/42) and in contact with the second shielding portion(11a/11), wherein the current spreading layer has the first conductivity type(n-type)[0160], and a doping concentration of the current spreading layer is greater than a doping concentration of the epitaxial layer(43/42); and second heavily doped portions that extend downward from the top surface of the epitaxial layer(43/42), wherein the second heavily doped portions have the second conductivity type(p-type)[0078] and act as a source region and a drain region[0089] of the third device.
Re claim 14 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 13, wherein the second shielding portion(11a/11) is in direct contact with a bottom surface of the current spreading layer and covers the bottom surface of the current spreading layer.
Re claim 15 Kawada and Sakai and Harrington disclose the semiconductor device as claimed in claim 11, wherein the second device is an NMOS device, the third device is a PMOS device, and the second device and the third device form a complementary metal-oxide-semiconductor (CMOS) device, wherein the CMOS device acts as a switching device that controls the first device.
Re claim 16 Kawada discloses a method for forming a semiconductor device, comprising: providing a substrate(40) that has a first conductivity type(n-type)[0160]; forming an epitaxial layer(43/42) on the substrate(40), wherein the epitaxial layer(43/42) has the first conductivity type(n-type)[0160]; forming a first device in a first region of the epitaxial layer(43/42) and forming a second device in a second region of the epitaxial layer(43/42), wherein the second device is separated from the first device and electrically connected to the first device, and wherein the first device comprises: a first trench gate structure(left 7/right 7) that extends downward from a top surface of the epitaxial layer(43/42) into the epitaxial layer(43/42), wherein the substrate(40) functions as a drain region[0089] of the first device; and a first shielding portion(11a/11) that is positioned below the first trench gate structure(left 7/right 7) and in contact with a bottom portion of the first trench gate structure(left 7/right 7), wherein the first shielding portion(11a/11) has a second conductivity type(p-type)[0078]; and wherein the second device comprises: a second trench gate structure(left 7/right 7) that extends downward from the top surface of the epitaxial layer(43/42) into the epitaxial layer(43/42); and a second shielding portion(11a/11) that is positioned under the second trench gate structure(left 7/right 7) and in contact with a bottom portion of the second trench gate structure(left 7/right 7), wherein the second shielding portion(11a/11) has the second conductivity type(p-type)[0078].
Kawada does not discloses a planar gate structure that is formed over the top surface of the epitaxial layer(43/42); wherein the first trench gate structure and the second trench gate structure are split-trench gate structures, and each of the split-trench gate structures comprises a bottom conductive portion and an insulating layer that covers sidewalls of the bottom conductive portion, and wherein the bottom conductive portion of the first trench gate structure is at least partially in direct contact with the first shielding portion, and the bottom conductive portion of the second trench gate structure is at least partially in direct contact with the second shielding portion.
Sakai discloses a planar gate structure(GE) that is formed over the top surface of the epitaxial layer(EP1/EP2);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sakai to the teachings of Kawada in order to enhance the reliability of semiconductor device [0006, Sakai].
Kawada does not discloses wherein the first trench gate structure and the second trench gate structure are split-trench gate structures, and each of the split-trench gate structures comprises a bottom conductive portion and an insulating layer that covers sidewalls of the bottom conductive portion, and wherein the bottom conductive portion of the first trench gate structure is at least partially in direct contact with the first shielding portion, and the bottom conductive portion of the second trench gate structure is at least partially in direct contact with the second shielding portion.
Harrington discloses in Fig 11 wherein the first trench gate structure(left/right 686)[0205] and the second trench gate structure(left/right 686)[0205] are split-trench gate structures, and each of the split-trench gate structures comprises a bottom conductive portion and an insulating layer(663/662) that covers sidewalls of the bottom conductive portion, andwherein the bottom conductive portion of the first trench gate structure is at least partially in direct contact with the first shielding portion(left/right 670), and the bottom conductive portion of the second trench gate structure is at least partially in direct contact with the second shielding portion(left/right 670).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Harrington to the teachings of Kawada in order to provide enhanced performance [0007, Harrington].
Re claim 17 Kawada and Sakai and Harrington disclose the method for forming a semiconductor device as claimed in claim 16, wherein the first shielding portion(11a/11) and the second shielding portion(11a/11) are formed in the same process.
Re claim 18 Kawada and Sakai and Harrington disclose the method for forming a semiconductor device as claimed in claim 16, wherein the first trench gate structure(left 7/right 7) and the second trench gate structure(left 7/right 7) are formed in the same process.
Re claim 19 Kawada and Sakai and Harrington disclose the method for forming a semiconductor device as claimed in claim 16, wherein after the first shielding portion(11a/11) and the second shielding portion(11a/11) are formed, the method further comprises: forming a current spreading layer in the first region, wherein the current spreading layer is formed in the epitaxial layer(43/42) and extends downward from the top surface of the epitaxial layer(43/42) to connect the first shielding portion(11a/11), wherein the current spreading layer has the first conductivity type(n-type)[0160], and a doping concentration of the current spreading layer is greater than a doping concentration of the epitaxial layer(43/42); forming a body region in the current spreading layer, wherein the body region extends downward from the top surface of the epitaxial layer(43/42), and the body region has the second conductivity type(p-type)[0078]; and forming a well region in the second region, wherein the well region extends downward from the top surface of the epitaxial layer(43/42) to contact the second shielding portion(11a/11).
Re claim 20 Kawada and Sakai and Harrington disclose the method for forming a semiconductor device as claimed in claim 19, wherein after the current spreading layer, the body region and the well region are formed, the method further comprises: forming first heavily doped portions simultaneously in the body region that is positioned in the first region and in the well region that is positioned in the second region, wherein the first heavily doped portions have the first conductivity type(n-type)[0160] and act as a source region of the first device and a drain region[0089] and a source region of the second device; and forming second heavily doped portions simultaneously in the body region that is positioned in the first region and in the well region that is positioned in the second region, wherein the second heavily doped portions have the second conductivity type(p-type)[0078] and act as bulk regions of the first device and the second device.
Re claim 21 Kawada and Sakai and Harrington disclose the method for forming a semiconductor device as claimed in claim 20, wherein after the current spreading layer, the body region, the well region, the first heavily doped portions and the second heavily doped portions are formed, the first trench gate structure(left 7/right 7) is formed in the first region and the second trench gate structure(left 7/right 7) is formed in the second region.
Re claim 23 Kawada and Sakai and Harrington disclose the method for forming a semiconductor device as claimed in claim 16, further comprising: forming a third device in a third region of the epitaxial layer(43/42), wherein the third device is separated from the first device and electrically connected to the second device, wherein the second shielding portion(11a/11) that is under the second trench gate structure(left 7/right 7) extends continuously to the third region.
Re claim 24 Kawada and Sakai and Harrington disclose the method for forming a semiconductor device as claimed in claim 23, wherein the third device further comprises: a third trench gate structure(left 7/right 7) that extends downward from the top surface of the epitaxial layer(43/42) into the epitaxial layer(43/42), wherein a bottom portion of the third trench gate structure(left 7/right 7) is in contact with the second shielding portion(11a/11).
Re claim 25 Kawada and Sakai and Harrington disclose the method for forming a semiconductor device as claimed in claim 24, wherein the first trench gate structure(left 7/right 7), the second trench gate structure(left 7/right 7) and the third trench gate structure(left 7/right 7) are formed in the same process.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 4-21, 23-25 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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