DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-17 in the reply filed on 07/28/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/28/2026 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (2023/0071998).
Re claim 1, Wang teaches a semiconductor device (Figs. 1-15), comprising: a first semiconductor structure (12) including a lower portion (Fig. 15) and an upper portion (Fig. 15), wherein the first semiconductor structure (12) has a first conductive type ([17], p-type); a second semiconductor structure (28) in contact with the lower portion of the first semiconductor structure (12), wherein the second semiconductor structure (28) has a second conductive type ([23], n-type) opposite to the first conductive type (p-type); and a third semiconductor structure (30) in contact with the lower portion of the first semiconductor structure (12), wherein the third semiconductor structure (30) has the second conductive type ([23], n-type), wherein the second semiconductor structure (28) and the third semiconductor structure (30) laterally extend toward opposite directions (Fig. 15).
Re claim 2, Wang teaches the semiconductor device of claim 1, further comprising: a first metal structure (40) in electrical contact with the second semiconductor structure (28); and a second metal structure (40) in electrical contact with the third semiconductor structure (30).
Re claim 3, Wang teaches the semiconductor device of claim 2, wherein the first semiconductor structure (12) is laterally interposed (Fig. 15) between the first and second metal structures (40), but is electrically isolated (32) from each of the first and second metal structures (40).
Re claim 7, Wang teaches the semiconductor device of claim 2, further comprising: a first contact electrode (36) vertically extending to contact the upper portion of the first semiconductor structure (12); a second contact electrode (42) vertically extending to contact the first metal structure (40); and a third contact electrode (42) vertically extending to contact the second metal structure (40).
Re claim 8, Wang teaches the semiconductor device of claim 1, wherein the first semiconductor structure (12), the second semiconductor structure (28), and the third semiconductor structure (30) operatively serve as a base, a collector, and an emitter of a bipolar junction transistor, respectively [34].
Re claim 9, Wang teaches the semiconductor device of claim 1, wherein the first semiconductor structure (12), the second semiconductor structure (28), and the third semiconductor structure (30) are each an epitaxially grown semiconductor structure [17, 23]. Claim(s) 10-15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (2023/0071998).
Re claim 10, Wang teaches a semiconductor device (Figs. 1-15), comprising: a first semiconductor structure (12) having a first conductive type ([17], p-type), the first semiconductor structure (12) comprising an upper portion and a lower portion (Fig. 15); a second semiconductor structure (28) having a second conductive type ([23], n-type) opposite to the first conductive type (p-type); a third semiconductor structure (30) having the second conductive type ([23], n-type), wherein the lower portion of the first semiconductor structure (12) is disposed between the second semiconductor structure (28) and the third semiconductor structure (30) and is in electrical contact (Fig. 15) with the second semiconductor structure (28) and the third semiconductor structure (30).
Re claim 11, Wang teaches the semiconductor device of claim 10, further comprising: a first metal structure (40) in electrical contact with the second semiconductor structure (28); and a second metal structure (40) in electrical contact with the third semiconductor structure (30).
Re claim 12, Wang teaches the semiconductor device of claim 11, wherein the second semiconductor structure (28) and the third semiconductor structure (30) physically isolate (Fig. 15) the lower portion of the first semiconductor structure (12) from the first metal structure (40) and the second metal structure (40).
Re claim 13, Wang teaches the semiconductor device of claim 11, further comprising: a first dielectric structure (32) disposed between the upper portion of the first semiconductor structure (12) and the first metal structure (40); and a second dielectric structure (32) disposed between the upper portion of the first semiconductor structure (12) and the second metal structure (40).
Re claim 14, Wang teaches the semiconductor device of claim 11, wherein the first dielectric structure (32) and the second dielectric structure (32) physically isolate (Fig. 15) the upper portion of the first semiconductor structure (12) from the first metal structure (40) and the second metal structure (40).
Re claim 15, Wang teaches the semiconductor device of claim 11, further comprising: a first contact electrode (36) vertically extending to contact the upper portion of the first semiconductor structure (12); a second contact electrode (42) vertically extending to contact the first metal structure (40); and a third contact electrode (42) vertically extending to contact the second metal structure (40). Re claim 17, Wang teaches the semiconductor device of claim 10, wherein the first semiconductor structure (12), the second semiconductor structure (28), and the third semiconductor structure (30) are each an epitaxially grown semiconductor structure [14, 23].
Allowable Subject Matter
Claims 4-6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 4, Wang teaches the semiconductor device of claim 3, yet remains explicitly silent to further comprising: a first dielectric structure extending along a first sidewall of the upper portion of the first semiconductor structure to electrically isolate the first semiconductor structure from the first metal structure; and a second dielectric structure extending along a second sidewall of the upper portion of the first semiconductor structure to electrically isolate the first semiconductor structure from the second metal structure.
Re claim 5, Wang teaches the semiconductor device of claim 2, yet remains explicitly silent to wherein the first metal structure is in contact with a top surface, a bottom surface, and a first sidewall of the second semiconductor structure; and the second metal structure is in contact with a top surface, a bottom surface, and a first sidewall of the third semiconductor structure.
Claim 6 is objected to for at least depending from objected claim 5. Re claim 16, Wang teaches the semiconductor device of claim 10, yet remains explicitly silent to wherein a lateral dimension of the lower portion of the first semiconductor structure is greater than a lateral dimension of the upper portion of the first semiconductor structure.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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