DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al. (2009/0250736).
Re claim 1, Yoon teaches a semiconductor device (Figs. 27-29), comprising: a semiconductor substrate (100) including a first area and a second area (Fig. 27); a first semiconductor structure (140a) disposed in the first area (“first area”), vertically extending [178-179], and separated from the semiconductor substrate (100) with a first dielectric structure (106) interposed therebetween (Fig. 29); a first transistor (160) disposed around the first semiconductor structure (140a), with the first semiconductor structure (140a) serving as a channel [139] of the first transistor (160); a second semiconductor structure (162) disposed in the second area (“second area”), vertically extending (Fig. 27), and in contact with the semiconductor substrate (100); and a second transistor (160, “second area”) disposed above the second semiconductor structure (162), with a third semiconductor structure (“portion of 162 between 174a and 174b and adjacent to 170”) laterally extending and serving as a channel [173] of the second transistor (160, “second area”).
Re claim 2, Yoon teaches the semiconductor device of claim 1, further comprising a second dielectric structure (168) interposed between the second transistor (160, “second area”) and the second semiconductor structure (162).
Re claim 3, Yoon teaches the semiconductor device of claim 1, wherein the second transistor is disposed laterally next to the first transistor and vertically above the first transistor (Fig. 29).
Re claim 4, Yoon teaches the semiconductor device of claim 1, wherein the first transistor further comprises: a first source/drain structure (143) surrounding a first portion (“lower portion”) of the first semiconductor structure (140a); a first gate structure (154) surrounding a second portion (“side portion”) of the first semiconductor structure (140a); a second source/drain structure (156) surrounding a third portion (“upper portion”) of the first semiconductor structure (140a). Re claim 5, Yoon teaches the semiconductor device of claim 4, wherein the first source/drain structure (143) is disposed below (Fig. 29) the first gate structure (154) and the first gate structure (154) is disposed below (Fig. 29) the second source/drain structure (156).
Re claim 6, Yoon teaches the semiconductor device of claim 5, wherein the first source/drain structure (143) laterally extends (Fig. 29) from the first semiconductor structure (140a) farther away than the first gate structure (154) laterally extends from the first semiconductor structure (140a), and the first gate structure (154) laterally extends from the first semiconductor structure (140a) farther away than the second source/drain structure (156) laterally extends (Fig. 29) from the first semiconductor structure (140a).
Re claim 7, Yoon teaches the semiconductor device of claim 1, wherein the second transistor (160, “second area”) further comprises: a third source/drain structure (174a) vertically extending and in contact with a first end (“left end”) of the third semiconductor structure (“portion of 162 between 174a and 174b and adjacent to 170”); a second gate structure (170) surrounding the third semiconductor structure (“portion of 162 between 174a and 174b and adjacent to 170”); a fourth source/drain structure (174b) vertically extending and in contact with a second end (“right end”) of the third semiconductor structure (“portion of 162 between 174a and 174b and adjacent to 170”).
Re claim 8, Yoon teaches the semiconductor device of claim 1, wherein each of the first semiconductor structure (140a) and the second semiconductor structure (162) is an epitaxially grown structure [103, 181] from the semiconductor substrate (100).
Claim(s) 10-12, 14, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al. (2009/0250736). Re claim 10, Yoon teaches semiconductor device (Figs. 27-29), comprising: a first transistor (160) comprising: a first semiconductor structure (140a) vertically extending away and separated from the semiconductor substrate (100); a first source/drain structure (143) surrounding the first semiconductor structure (140a); a first gate structure (154) surrounding the first semiconductor structure (140a) and disposed above the first source/drain structure (143); and a second source/drain structure (156) surrounding the first semiconductor structure (140a) and disposed above the first gate structure (154); and a second transistor (160, “second area”) disposed above a second semiconductor structure (162) that vertically extends and is in contact with the semiconductor substrate (100), and comprising: a third semiconductor structure (“portion of 162 between 174a and 174b and adjacent to 170”) laterally extending (Fig. 29); a third source/drain structure (174a) in contact with a first end (“left end”) of the third semiconductor structure (“portion of 162 between 174a and 174b and adjacent to 170”); a second gate structure (170) surrounding the third semiconductor structure (“portion of 162 between 174a and 174b and adjacent to 170”); and a fourth source/drain structure (174b) in contact with a second end (“right end”) of the third semiconductor structure (“portion of 162 between 174a and 174b and adjacent to 170”). Re claim 11, Yoon teaches the semiconductor device of claim 10, further comprising: a first dielectric structure (106) vertically interposed between the first semiconductor structure (140a) and the semiconductor substrate (100); and a second dielectric structure (168) vertically interposed between the second semiconductor structure (162) and the second gate structure (170).
Re claim 12, Yoon teaches the semiconductor device of claim 11, wherein the second dielectric structure (168) is disposed vertically above the first dielectric structure (106).
Re claim 14, Yoon teaches the semiconductor device of claim 10, each of the first semiconductor structure (140a) and the second semiconductor structure (162) is an epitaxially grown structure [103, 1865] from the semiconductor substrate (100).
Re claim 16, Yoon teaches the semiconductor device of claim 10, wherein the first source/drain structure (143) laterally extends (Fig. 29) from the first semiconductor structure (140a) farther away than the first gate structure (154) laterally extends from the first semiconductor structure (140a), and the first gate structure (154) laterally extends from the first semiconductor structure (140a) farther away than the second source/drain structure (156) laterally extends (Fig. 29) from the first semiconductor structure (140a).
Re claim 17, Yoon teaches the semiconductor device of claim 10, wherein the first transistor (160) has a first conductivity type [186], and the second transistor (160, “second area”) has a second, opposite conductivity type [186].
Prior art of record
Re claim 18, Yoon et al. (2009/0250736) teaches a method for fabricating semiconductor devices (Figs. 27-29), comprising: epitaxially growing a first semiconductor structure (140a) and a second semiconductor structure (162) from a semiconductor substrate (100), forming a first transistor (160) around the first semiconductor structure (140a). Yoon does not explicitly teach wherein the first and second semiconductor structures each extend in a vertical direction with a same height; replacing a bottom portion of the first semiconductor structure with a first dielectric structure; epitaxially growing first, second, third, and fourth semiconductor layers over the second semiconductor structure; replacing the first semiconductor layer with a second dielectric structure; and forming a second transistor above the second dielectric structure.
Allowable Subject Matter
Claims 9, 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 9, Yoon teaches the semiconductor device of claim 1, yet remains explicitly silent to wherein the first and second semiconductor structures have a first conductivity type, and the third semiconductor structure has a second, opposite conductivity type.
Re claim 13, Yoon teaches the semiconductor device of claim 11, yet remains explicitly silent to wherein the first dielectric structure has its sidewall aligned with a sidewall of the first semiconductor structure, and the second dielectric structure has its sidewall aligned with a sidewall of the second semiconductor structure.
Re claim 15, Yoon teaches the semiconductor device of claim 10, yet remains explicitly silent to wherein the first and second semiconductor structures have a first conductivity type, and the third semiconductor structure has a second, opposite conductivity type.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not anticipate or make obvious the method of claim 18, including each of the limitations and specifically wherein the first and second semiconductor structures each extend in a vertical direction with a same height; replacing a bottom portion of the first semiconductor structure with a first dielectric structure; epitaxially growing first, second, third, and fourth semiconductor layers over the second semiconductor structure; replacing the first semiconductor layer with a second dielectric structure; and forming a second transistor above the second dielectric structure, for the same reasons as mentioned for claim 18 in the prior art of record above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gardner et al. (2022/0254925), Figs. 1A-10; Gardner et al. (2022/0238652), Figs. 1-9G; Gardner et al. (2022/0102492), Figs. 1-35; Gardner et al. (2021/0366904), Figs. 1-22; Sun et al. (2012/0319201), Figs. 3A-43C; Manda et al. (2010/0308385), Figs. 1A-5H. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached on M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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