DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 7 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae et al. (2023/0068706). Re claim 1, Bae teaches a semiconductor device (Figs. 1-3), comprising: a first gate structure (110, 160) comprising a first gate electrode (110) and a ferroelectric layer (160); a second gate structure (131, 170) comprising a second gate electrode (131) and a gate dielectric layer (170); and a semiconductor layer (140) disposed between the ferroelectric layer (160) and the gate dielectric layer (170), wherein the first gate structure (110, 160), the semiconductor layer (140), and the second gate structure (131, 170) are arranged concentrically (Fig. 3).
Re claim 2, Bae teaches the semiconductor device of claim 1, wherein the semiconductor layer (140) surrounds an outer sidewall of the first gate structure (11, 160).
Re claim 4, Bae teaches the semiconductor device of claim 1, wherein the semiconductor layer (140) comprises a conductive oxide material (“IGZO”, [70]).
Re claim 5, Bae teaches the semiconductor device of claim 1, wherein a bottom portion (Fig. 1) of the semiconductor layer (140) extends along a bottom portion (Fig. 1) of the gate dielectric layer (170).
Re claim 7, Bae teaches the semiconductor device of claim 1, further comprising: a first source/drain contact (102) electrically coupled to a bottom portion (Fig. 1) of the semiconductor layer (140); and a second source/drain contact (103) electrically coupled to a top portion (Fig. 1) of the semiconductor layer (140).
Re claim 9, Bae teaches the semiconductor device of claim 7, wherein a portion (Fig. 1) of the first source/drain contact (102) is below the ferroelectric layer (160).
Claim(s) 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae et al. (2023/0068706).
Re claim 16, Bae teaches a method (Figs. 1-3), comprising: forming a first gate structure (110, 160) over a substrate (101), the first gate structure (110, 160) comprising a first gate electrode (110) and a ferroelectric layer (160); forming a second gate structure (131, 170) comprising a second gate electrode (131) and a gate dielectric layer (170); and forming a semiconductor layer (140) sandwiched between the ferroelectric layer (160) and the gate dielectric layer (170), wherein the first gate structure (110, 160), the semiconductor layer (140), and the second gate structure (131, 170) are formed concentrically (Fig. 3).
Prior art of record
Re claim 10, Lee et al. (2023/0309314) teaches a semiconductor device (Figs. 18-19), comprising: an inner gate structure (240, 230) comprising an inner gate electrode (240) disposed over a ferroelectric layer (230); a semiconductor layer (176) wrapping around the inner gate structure (240, 230) and comprising a conductive oxide [33]. Lee further teaches a second gate electrode (332).
Lee does not explicitly teach an outer gate structure wrapping around the semiconductor layer, the outer gate structure comprising a second gate electrode disposed over a gate dielectric layer, wherein the inner gate structure, the semiconductor layer, and the outer gate structure are arranged concentrically.
Allowable Subject Matter
Claims 3, 6, 8 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 3, Bae teaches the semiconductor device of claim 1, yet remains explicitly silent to wherein the semiconductor layer surrounds an outer sidewall of the second gate structure. Re claim 6, Bae teaches the semiconductor device of claim 1, yet remains explicitly silent to further comprising: a first intermediate dielectric layer extending between the ferroelectric layer and the semiconductor layer; and a second intermediate dielectric layer extending between the semiconductor layer and the gate dielectric layer.
Re claim 8, Bae teaches the semiconductor device of claim 7, yet remains explicitly silent to wherein an entirety of the first source/drain contact is adjacent to a sidewall of the ferroelectric layer.
Re claim 17, Bae teaches the method of claim 16, yet remains explicitly silent to wherein: the step of forming the first gate structure comprises: forming an opening over the substrate, depositing the ferroelectric layer in the opening, and depositing the first gate electrode over the ferroelectric layer to fill the opening, the step of forming the semiconductor layer comprises depositing the semiconductor layer over the ferroelectric layer, and the step of forming the second gate structure comprises: depositing the gate dielectric layer over the semiconductor layer; and forming the second gate electrode over the gate dielectric layer. Claim 18 is objected to for at least depending from objected claim 17.
Re claim 19, Bae teaches method of claim 16, yet remains explicitly silent to wherein: the step of forming the first gate structure comprises: forming an opening over the substrate, forming the first gate electrode within the opening, and depositing the ferroelectric layer over the first gate electrode in the opening, the step of forming the semiconductor layer comprises depositing the semiconductor layer over the ferroelectric layer in the opening, and the step of forming the second gate structure comprises: depositing the gate dielectric layer over the semiconductor layer, and forming the second gate electrode over the gate dielectric layer to fill the opening.
Claim 20 is objected to for at least depending from objected claim 19.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not anticipate or make obvious the device of claim 10, including each of the limitations and specifically an outer gate structure wrapping around the semiconductor layer, the outer gate structure comprising a second gate electrode disposed over a gate dielectric layer, wherein the inner gate structure, the semiconductor layer, and the outer gate structure are arranged concentrically, for the same reasons as mentioned for claim 10 in the prior art of record above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu (2019/0123061), Figs. 1-6M; Zhang et al. (2016/0163729), Figs. 1A-31. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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