Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/597,861 filed on 03/06/2024.
Election/Restrictions
Applicant’s election with traverse of Species 2 (claims 1-20) in the reply filed on 02/11/2026 is acknowledged. The ground of traversal is as follows. As set forth in MPEP 806.04(f), restriction among species is proper only where the species are mutually exclusive. The processes illustrated in FIGS. 2A-2B, 3A-3B, and 4A-4B represent sequential stages of a single method of forming a semiconductor-on-insulator (SOI) substrate and are therefore not mutually exclusive. Furthermore, the claims define the same essential characteristics of a single inventive process. As stated in MPEP 806.03, where the claims define the same essential characteristics of a single disclosed embodiment, restriction should never be required.
Applicant’s traversal of the restriction requirement has been fully considered and is found to be persuasive, as the previously identified groups are not mutually exclusive. Therefore, all of claims 1-20 are considered and treated on the merits.
In the spirit of compact prosecution, the prior restriction requirement is hereby withdrawn and Species I - III of the prior restriction requirement are hereby rejoined for treatment on the merits.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 8 recites “a buffer layer further comprising a boron diffusion inhibiter.” However, the specification only discloses that the buffer layer may include a diffusion inhibitor such as carbon (see, e.g., ¶0018).
The specification does not describe or reasonably convey to one of ordinary skill in the art that the inventor was in possession of a diffusion inhibitor specifically for inhibiting boron diffusion, nor does it identify carbon as functioning to inhibit boron diffusion.
Accordingly, the limitation “boron diffusion inhibiter” lacks adequate written description support in the specification. Therefore, claim 1 is rejected under 35 U.S.C. 112(a).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites “…splitting the epitaxial layer into a first split buffer layer and a second split buffer layer...” in lines 10-11. However, the claim initially recites an epitaxial layer, but then refers to resulting layers as “buffer layers,” which are different structures and are not clearly defined as corresponding to the epitaxial layer.
It is unclear whether the “first split buffer layer” and “second split buffer layer” are intended to be portions of the epitaxial layer or separate buffer layers. Thus, the metes and bounds of the claim are unclear.
Accordingly, claim 18 is rejected under 35 U.S.C. 112(b) as being indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 10-11 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2004/0005740 to Lochtefeld et al. (Lochtefeld).
Regarding independent claim 1, Lochtefeld discloses a method of forming a (SOI) substrate (Figs. 3-4), comprising:
forming a buffer layer (16) over a substrate (14, see figure. 3 with respect to figure. 1B embodiment);
forming a semiconductor layer (19, see Fig. 3 with respect to Fig. 1B, it is noted that Fig. 3 shows the bonding step specifically for the figure. 1A embodiment, however, when the Figure. 1B embodiment is bonded as shown in figure. 3, a layer 19 is present between 16 and 18 as shown in figure 1B) over the buffer layer (16);
forming an ion implantation region (see ¶0049) in the buffer layer (16);
forming a bonding layer (Fig. 3: 18) over the buffer layer (16);
bonding the bonding layer (18) to a semiconductor structure (Fig. 3: 50 it is noted that handle wafer 50 includes a dielectric layer 52 disposed over a semiconductor substrate 54);
performing a splitting process (¶0049) along the ion implantation region (20) in the buffer layer (16), leaving the semiconductor layer (19) and a first split buffer layer (80, 80 is a remaining portion of the buffer layer 16) on the semiconductor structure (50) (see Fig. 4); and
removing the first split buffer layer (80; Fig. 5 and ¶0050) from the semiconductor layer (19; it is noted that a layer 19 is present between 16 and 18 as shown in figure 1B), wherein after removing the first split buffer layer (80; Fig. 5), the semiconductor structure (50), the bonding layer (18), and the semiconductor layer (19; it is noted that a layer 19 is present between 16 and 18 as shown in figure 1B) constitute the SOI substrate (see Fig. 6 and ¶0053).
Regarding claim 2, Lochtefeld discloses wherein the semiconductor structure (50) comprises a semiconductor substrate (54) and a bonding dielectric layer (52) formed on the semiconductor substrate (54, see Fig. 3: 50), wherein the bonding layer (18) is bonding to the bonding dielectric layer (52) through a dielectric-to-dielectric bonding (Fig. 4 and ¶0049).
Regarding claim 3, Lochtefeld discloses wherein the bonding dielectric layer (52) is formed by a thermal oxidation process (¶0047), and the bonding layer (18) is formed by a chemical vapor deposition process (¶0038).
Regarding claim 4, Lochtefeld discloses wherein the splitting process splits the buffer layer (16) into the first split buffer layer (80) on the semiconductor layer (19; it is noted that a layer 19 is present between 16 and 18 as shown in figure 1B) and a second split buffer layer (82) on the substrate (54) (see Fig. 4).
Regarding claim 6, Lochtefeld discloses wherein the buffer layer (16) comprises silicon germanium (¶0035).
Regarding claim 7, Lochtefeld discloses wherein the buffer layer (16) further comprises boron (¶0036).
Regarding claim 10, Lochtefeld discloses forming a sacrificial layer (Fig. 2B: 22 and ¶0046) on the semiconductor layer (18) and removing the sacrificial layer (22 is planarized) after forming the ion implantation region (20) in the buffer layer (16).
Regarding independent claim 11, Lochtefeld discloses a method of forming a SOI substrate (Figs. 3-4), comprising:
providing a first initial structure (Fig.3: 50), wherein the first initial structure (50) comprises:
a first substrate (54); and
a first bonding layer (52), disposed over the first substrate (54);
providing a second initial structure (Fig. 3: 8), wherein the second initial structure (8) comprises:
a second substrate (14, see figure. 3 with respect to figure. 1A or 1B embodiment);
a buffer layer (16), disposed over the second substrate (14), wherein the buffer layer (16) comprises a cleavage plane (20) formed by implanting an implantation species into the buffer layer (16, see ¶0049);
a semiconductor layer (19, see Fig. 3 with respect to Fig. 1B) disposed over the buffer layer (16), wherein a position in the buffer layer where the implantation species has the highest concentration is at a greater distance from the semiconductor layer than from the second substrate (Fig. 3 shows the bonding step specifically for the figure. 1A embodiment, however, when the Figure. 1B embodiment is bonded as shown in figure. 3, a layer 19 is present between 16 and 18 as shown in figure 1B); and
a second bonding layer (Fig. 3: 18), disposed over the semiconductor layer (19);
bonding (Fig. 3 and ¶0047) the second bonding layer (18) of the second initial structure (8) to the first bonding layer (52) of the first initial structure (50);
performing a splitting process (¶0049) along the cleavage plane (20) in the buffer layer (16); and
after performing the splitting process (Fig. 4 and ¶0049), performing a post annealing process on the first substrate (¶0049 discloses wafer 70 (which includes the first substrate 54) with strained layer 18 is annealed further).
Regarding claim 16, Lochtefeld discloses wherein performing the splitting process (Fig. 4) to split the buffer layer (16) into a first split buffer layer (80) on the semiconductor layer (19; Fig. 3 shows the bonding step specifically for the figure. 1A embodiment, however, when the Figure. 1B embodiment is bonded as shown in figure. 3, a layer 19 is present between 16 and 18 as shown in figure 1B) and a second split buffer layer (82) on the second substrate (14).
Regarding claim 17, Lochtefeld discloses wherein the splitting process (Fig. 4) is induced at the cleavage plane by an annealing process (¶0049), and the annealing process forms a hydrogen exfoliation layer along the cleavage plane in the buffer layer (16 and ¶0049).
Regarding independent claim 18, Lochtefeld discloses a method of forming a SOI substrate (Figs. 3-4), comprising:
forming a first bonding layer (Fig. 3: 52) over a carrier substrate (54);
forming an epitaxial layer (16) over a substrate (12);
forming a semiconductor layer (19; it is noted that Fig. 3 shows the bonding step specifically for the figure. 1A embodiment, however, when the Figure. 1B embodiment is bonded as shown in figure. 3, a layer 19 is present between 16 and 18 as shown in figure 1B) over the epitaxial layer (16);
implanting (¶0044) an implantation species into the epitaxial layer (16), so as to define a cleavage plane (20) in the epitaxial layer (16; ¶0044 and see Fig. 3 with respect to Fig. 2A);
forming a second bonding layer (18) over the semiconductor layer (19; layer 19 is present between 16 and 18 as shown in figure 1B);
bonding the second bonding layer (18) to the first bonding layer (52); and
performing an annealing process to form a hydrogen exfoliation layer along the cleavage plane in the epitaxial layer (16 and ¶0049), and splitting the epitaxial layer (16) into a first split buffer layer (80; 80 is a first portion of epitaxial layer 16) and a second split buffer layer (82, 82 is a second portion of epitaxial layer 16) along the hydrogen exfoliation layer (¶0049).
Regarding claim 19, Lochtefeld discloses forming a sacrificial layer (Fig. 2B: 22) on the semiconductor layer (19) and after implanting the implantation species into the epitaxial layer (16), removing the sacrificial layer (22; 22 is planarized).
Regarding claim 20, Lochtefeld discloses wherein the semiconductor layer (19; it is noted that Fig. 3 shows the bonding step specifically for the figure. 1A embodiment, however, when the Figure. 1B embodiment is bonded as shown in figure. 3, a layer 19 is present between 16 and 18 as shown in figure 1B) is protected by the sacrificial layer (22) during implanting the implantation species into the epitaxial layer (16; ¶0046 discloses the sacrificial layer 22 is formed over the semiconductor layer 19 and the second bonding layer 18 (under BRI) prior to ion implantation into relaxed layer 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2004/0005740 to Lochtefeld et al. (Lochtefeld).
Regarding claim 5, Lochtefeld discloses wherein the first split buffer layer (80) is formed on the second split buffer layer.
Lochtefeld fails to explicitly disclose the first split buffer layer (80) is formed to be thicker than the second split buffer layer.
It is known in the art to use thickness for the buffer layer in the semiconductor later or substrate. It would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the thickness of the buffer layer to be thicker in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thicker or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding claims 12-13, Lochtefeld discloses wherein performing an implantation process to implant the implantation species through a sacrificial layer (Fig. 2B: 19) into the buffer layer (16), so as to define the cleavage plane (20) in the buffer layer (16).
Lochtefeld fails to explicitly disclose after performing the implantation process, a concentration of the implantation species comprised in the semiconductor layer is less than a concentration of the implantation species comprised in the second substrate and (as recites in claim 13, wherein a concentration of the implantation species in the semiconductor layer is zero).
It is known in the art to use concentration of the implantation species in the semiconductor later or substrate. It would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the concentration of the implantation species in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed concentration or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding claim 14, Lochtefeld discloses wherein providing the second initial structure comprises:
forming the buffer layer (16) on the second substrate (12);
forming the semiconductor layer (14) on the buffer layer (16);
forming a sacrificial layer (Fig. 1B: 19) on the semiconductor layer (14);
performing an implantation process to implant the implantation species (¶0044) through the sacrificial layer (19) into the buffer layer (16), so as to define the cleavage plane (20) in the buffer layer (16);
removing the sacrificial layer (Fig. 3: 19); and
forming the second bonding layer (18) on the semiconductor layer (14).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2004/0005740 to Lochtefeld et al. (Lochtefeld) in view of WO 2009/040707 to DOORNBOS et al. (DOORNBOS).
Regarding claims 8-9, Lochtefeld fails to explicitly discloses wherein the buffer layer further comprises a boron diffusion inhibiter and wherein the boron diffusion inhibiter comprises carbon.
Doornbos discloses carbon will serve as a diffusion inhibiter (page, 8, lines 31-32 and page 9, line 1).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the buffer layer of Lochtefeld with the carbon as a diffusion inhibiter to slow down diffusion because it binds to silicon interstitials created by the amorphising implant of germanium (page 9, lines 5-8).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2004/0005740 to Lochtefeld et al. (Lochtefeld) in view of US Pub # 2019/0131400 to Wu et al. (Wu).
Regarding claim 15, Lochtefeld discloses wherein the first substrate comprises a semiconductor substrate (¶0047).
Lochtefeld fails to explicitly disclose a polysilicon layer formed on the semiconductor substrate.
Wu discloses a polysilicon layer (Fig. 3B: 201) formed on the semiconductor substrate (102).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor substrate of Lochtefeld with a polysilicon layer in order to trap carriers in the semiconductor substrate (¶0018).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 7781306 to Kakehata; US Pub # 2003/0036247 to Eriksen et al.; US Pub # 2022/0223467 to Reboh et al.; US Pub # 2020/0176306 to Cheng et al. US Pub # 2020/0127041 to Schwarzenbach et al.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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