Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18/597,876 filed on August 19, 2026.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The title of the invention has been amended as “Semiconductor Structure Comprising Multiple Thermal Vias and Manufacturing Method Thereof”.
Claim Objections
5. The objections of claims 1, 4 have been withdrawn, per the response dated on 08/19/2026.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Horiuchi et al. (US 2011/0012266 A1).
Regarding independent claim 1, Horiuchi et al. teaches a semiconductor structure (10, para [0050]), including (Fig. 3):
a substrate (13, para [0050]) having a plurality of thermal vias (11, para [0051] made of aluminum nitride material, considering as the thermal vias, as the applicant claimed the material in claim 2), wherein the plurality of thermal vias (11) penetrate the substrate (13);
an electronic component (14, para [0050]) disposed on the substrate (13); and
an interconnection structure (17a wiring layer, para [0050]) disposed on the substrate (13) and electrically connected to the electronic component (14),
wherein the plurality of thermal vias (11) of the substrate (13) are filled with a dielectric material (aluminum nitride, see para [0051]), and a thermal conductivity of the dielectric material is greater than 200 W/m*K (claim 2 recites ‘AlN/ aluminum nitride’ as the dielectric material, therefore, it is inherent that aluminum nitride material possesses the thermal conductivity greater than 200 W/m*K).
Regarding claim 2, Horiuchi et al. teaches wherein (Fig. 3), the dielectric material (inside the through holes 11) includes aluminum nitride (para [0051]), beryllium oxide, silicon carbide, diamond, or a combination thereof.
Regarding claim 3, Horiuchi et al. teaches wherein (Fig. 3), the electronic component (14) and the interconnection structure (17a) are disposed on a first surface of the substrate (13), and the plurality of thermal vias (11) are exposed by a second surface of the substrate (13), wherein the second surface is opposite to the first surface.
Regarding claim 4, Horiuchi et al. teaches wherein (Fig. 3), including at least one semiconductor die (14).
Examiner’s Note
9. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
10. It has been acknowledged that the applicant amended claims 1, 4, per the response dated on 08/19/2026.
Applicant’s remarks in pages 7-10 have been considered, but they are not found persuasive, because the applicant made argument on ‘though-holes’ 11 of the prior art which represent as the thermal vias or thermal plugs, because of filled dielectric material (same material- aluminum nitride) as the applicant claimed. In the rejection, the examiner has not considered element 12 as the thermal vias. This is to remind that these are device claims, and were rejected how they had been constructed.
Conclusion
11. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
13. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
Prosecution Insights