Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18/597,878 filed on July 22, 2026.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Objections
4. The objections of claims 12, 15, 17, 19 have been withdrawn per the response dated on 07/22/2026.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
8. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0310470 A1) in view of Wu et al. (US 2021/0366805 A1).
Regarding independent claim 1, Chen et al. teaches a semiconductor device, comprising (Fig. 33):
a primary semiconductor die (50B, para [0084]) with a top surface, wherein the top surface comprising a first region (middle portion) and a second region (two sides of the middle portion) besides the first region (middle portion);
an auxiliary semiconductor die (50A, para [0084]) attached onto the first region (middle portion) of the top surface of the primary semiconductor die (50B);
a thermally conductive laminated structure (92A/92B/92C/94A/94B/94C combinedly a thermally conductive structure) formed on the primary semiconductor die (50B) and the auxiliary semiconductor die (50A), wherein the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) at least partially covers the second region (two sides) of the top surface of the primary semiconductor die (50B), and at least partially covers a top surface of the auxiliary semiconductor die (50A); and
a heat spreader (208, para [0085]) thermally coupled to the primary semiconductor die (50B) and the auxiliary semiconductor die (50A) through at least the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C); wherein the heat spreader (208) comprises:
a lid (para [0056]) disposed on the auxiliary semiconductor die (50A) and thermally coupled to the auxiliary semiconductor die (50A) through the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) formed thereon, and
a first plurality of lateral portions (see the annotated figure below) that extend from the lid, and attached onto and thermally coupled to the second region (two sides) of the primary semiconductor die (50B) through the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) formed thereon.
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Chen et al. is silent to explicitly disclose wherein, the thermally conductive laminated structure formed on and in direct contact with the primary semiconductor die and the auxiliary semiconductor die.
Wu et al. discloses wherein (Fig. 2), the thermally conductive structure (400 TIM, para [0018]) formed on and in direct contact with the primary semiconductor die (100) and the auxiliary semiconductor die (140).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Wu et al. and modify the thermally conductive structure of Chen et al., in order to improve the heat dissipation for the block 100 (chip) (para [0035]).
Regarding claim 2, Chen et al. and Wu et al. teach all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) comprises a soldering type thermal interface layer (92: 92A TIM, para [0038]) and an adhesion layer (94: 94A).
Regarding claim 3, Chen et al. and Wu et al. teach all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the primary semiconductor die (50B) and the auxiliary semiconductor die (50A) are bonded together by hybrid bonding (product-by-process limitation, considered as limited weight in the device claim).
Regarding claim 4, Chen et al. and Wu et al. teach all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the first plurality of lateral portions (see the annotated figure below) that extend from the lid, and is attached onto and thermally coupled to the second region (two sides) of the primary semiconductor die (50B) through the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) formed thereon, and
the lid and the first plurality of lateral portions (see figure below) that are integrally formed as a single piece (208/lid/lateral portions are single structure).
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Chen et al. is silent to explicitly disclose wherein, the first plurality of lateral portions that extend vertically downward from the lid, and is attached onto and thermally coupled to the second region of the primary semiconductor die through the thermally conductive laminated structure formed thereon.
Wu et al. discloses wherein (Fig. 2), the first plurality of lateral portions that extend vertically downward from the lid (300), and is attached onto and thermally coupled to the second region (sides) of the primary semiconductor die (100) through the thermally conductive structure (400) formed thereon.
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Wu et al. and modify the structure of the heat spreader of Chen et al., in order to improve the lateral or vertical (upper or bottom) heat dissipation for the first die 110, the second die 120, the third die 130, or the fourth die 140 (para [0035]).
Regarding claim 5, Chen et al. and Wu et al. teach all of the limitations of claim 4 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), further comprising:
a substrate (110 called interposer, para [0085]), wherein the primary semiconductor die (50B) is attached on a top surface of the substrate (110); and
wherein the heat spreader (208) further comprises a second plurality of lateral portions (see the annotated figure in claim 4) that extend from the lid onto the top surface of the substrate (110) to support the heat spreader (208) on the substrate (110).
Regarding claim 6, Chen et al. and Wu et al. teach all of the limitations of claim 5 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the second plurality of lateral portions are spaced apart from the first plurality of lateral portions to form a cavity (see the annotated figure in claim 4) therebetween, the semiconductor device further comprises at least one electronic component (80B, para [0056]) received within the cavity and attached on the substrate (110), and wherein the at least one electronic component (80B) is thermally coupled to the lid of the heat spreader (208).
Regarding claim 7, Chen et al. and Wu et al. teach all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the first plurality of lateral portions (shown in the figure of claim 4) are attached to and thermally coupled to the lid through a thermally conductive layer (210), and attached onto and thermally coupled to the second region of the primary semiconductor die (50B) through the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) formed thereon.
Regarding claim 8, Chen et al. and Wu et al. teach all of the limitations of claim 7 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), further comprising:
a substrate (110 called interposer, para [0085]), wherein the primary semiconductor die (50B) is attached on a top surface of the substrate (110); and
wherein the heat spreader (208) further comprises a second plurality of lateral portions that extend from the lid onto the top surface of the substrate (110) to support the heat spreader (208) on the substrate (110).
Regarding claim 9, Chen et al. and Wu et al. teach all of the limitations of claim 8 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the second plurality of lateral portions are spaced apart from the first plurality of lateral portions to form a cavity (see the annotated figure in claim 4) therebetween, the semiconductor device further comprises at least one electronic component (80B) received within the cavity and attached on the substrate (110), and wherein the at least one electronic component (80B) is thermally coupled to the lid of the heat spreader (208).
Regarding claim 10, Chen et al. and Wu et al. teach all of the limitations of claim 7 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the thermally conductive layer (92: 92A) is a soldering type thermal interface layer (TIM).
Regarding independent claim 11, Chen et al. teaches a method for forming a semiconductor device, comprising (Figs. 30-33):
providing a semiconductor die stack (50B/50A, para [0084]) with a primary semiconductor die (50B) and an auxiliary semiconductor die (50A), wherein the primary semiconductor die (50B) comprises a top surface comprising a first region (middle) and a second region (sides) besides the first region, wherein the auxiliary semiconductor die (50A) is attached onto the first region (middle) of the top surface of the primary semiconductor die (50B);
forming a thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) on the semiconductor die stack (50B/50A), wherein the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) at least partially covers the second region of the top surface of the primary semiconductor die (50B), and at least partially covers a top surface of the auxiliary semiconductor die (50A); and
attaching a heat spreader (208, para [0085]) on the semiconductor die stack (50B/50A) through the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C), so that the heat spreader (208) is thermally coupled to the primary semiconductor die (50B) and the auxiliary semiconductor die (50A) through the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C); wherein the heat spreader (208) comprises a lid and a first plurality of lateral portions extending from the lid, and wherein attaching the heat spreader (208) on the semiconductor die stack (50B/50A) comprises:
disposing the lid on the auxiliary semiconductor die (50A), so that the lid is thermally coupled to the auxiliary semiconductor die (50A) through the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) formed thereon and
attaching the first plurality of lateral portions onto the second region of the primary semiconductor die (50B), so that the first plurality of lateral portions are thermally coupled to the second region (sides) of the primary semiconductor die (50B) through the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) formed thereon.
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Chen et al. is silent to explicitly disclose wherein, the thermally conductive laminated structure is in direct contact with and at least partially covers the second region of the top surface of the primary semiconductor die, and at least partially covers a top surface of the auxiliary semiconductor die;
the first plurality of lateral portions that extending vertically downward from the lid.
Wu et al. discloses wherein (Fig. 2), the thermally conductive structure (400 TIM, para [0018]) is in direct contact with and at least partially covers the second region (sides) of the top surface of the primary semiconductor die (100), and at least partially covers a top surface of the auxiliary semiconductor die (140);
the first plurality of lateral portions that extend vertically downward (shown in the figure below) from the lid (300).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Wu et al. and modify the structure of the heat spreader of Chen et al., in order to improve the lateral or vertical (upper or bottom) heat dissipation for the chip 100, the first die 110, the second die 120, the third die 130, or the fourth die 140 (para [0035]).
Regarding claim 12, Chen et al. and Wu et al. teach all of the limitations of claim 11 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), forming the thermally conductive laminated structure (92A/92B/92C/94A/94B/94C) comprises forming an adhesion layer (92: 92A) and forming a soldering type thermal interface layer (TIM).
Regarding claim 13, Chen et al. and Wu et al. teach all of the limitations of claim 11 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the primary semiconductor die (50B) and the auxiliary semiconductor die (50A) are bonded by hybrid bonding (see para [0065] wherein IC dies 50A or 50B is attached to the wafer 300 by hybrid bonding without the use of adhesive or solder, similarly ICs 50A and 50B in Fig, 33 bonded together).
Regarding claim 14, Chen et al. and Wu et al. teach all of the limitations of claim 11 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the lid and the first plurality of lateral portions are integrally formed as a single piece (208 is a single structure),
Regarding claim 15, Chen et al. and Wu et al. teach all of the limitations of claim 14 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), further comprising:
providing a substrate (110 called interposer, para [0085]); and
attaching the primary semiconductor die (50B) on a top surface of the substrate (110); wherein the heat spreader (208) further comprises a second plurality of lateral portions extending from the lid; and
wherein attaching the heat spreader (208) on the semiconductor die stack (50B/50A) further comprises: attaching the second plurality of lateral portions onto the top surface of the substrate (110) to support the heat spreader (208) on the substrate (110).
Regarding independent claim 16, Chen et al. teaches a method for forming a semiconductor device, comprising (Figs. 30-33):
providing a semiconductor die stack (50B/50A, para [0084]) with a primary semiconductor die (50B) and an auxiliary semiconductor die (50A), wherein the primary semiconductor die (50B) comprises a top surface comprising a first region (middle portion) and a second region (two sides) besides the first region, wherein the auxiliary semiconductor die (50A) is attached onto the first region (middle portion) of the top surface of the primary semiconductor die (50B);
forming an adhesion layer (92: 92A) on the semiconductor die stack (50B/50A), wherein the adhesion layer (92: 92A) at least partially covers the second region (two sides) of the top surface of the primary semiconductor die (50B) and the top surface of the auxiliary semiconductor die (50A);
forming a first soldering type thermal interface layer (94: 94A) on the second region of the top surface of the primary semiconductor die (50B);
attaching a thermally conductive block (94: 94B) on the first soldering type thermal interface layer (94A) to form a flat top surface above the semiconductor die stack (50B/50A);
forming a second soldering type thermal interface layer (94: 94C) on the flat top surface above the semiconductor die stack (50B/50A); and
attaching a lid (see the annotated figure below) onto the flat top surface above the semiconductor die stack (50B/50A) to form a heat spreader (208, para [0085]) at least using the lid and the thermally conductive block (94B) between the lid and the second region (right side) of the primary semiconductor die (50B), wherein the lid is thermally coupled to the primary semiconductor die (50B) through the thermally conductive block (94B), the first and second soldering type thermal interface layers (94A/94C) and the adhesion layer (92A), and thermally coupled to the auxiliary semiconductor die (50A) through the second soldering type thermal interface layer (94C) and the adhesion layer (92A).
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Chen et al. is silent to explicitly disclose wherein, the adhesion layer is in direct contact with and at least partially covers the second region of the top surface of the primary semiconductor die and the top surface of the auxiliary semiconductor die.
Wu et al. discloses wherein (Fig. 2), the adhesion layer (400) is in direct contact with and at least partially covers the second region of the top surface of the primary semiconductor die (100) and the top surface of the auxiliary semiconductor die (140).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Wu et al. and modify the thermally conductive structure of Chen et al., in order to improve the heat dissipation for the block 100 (chip) (para [0035]).
Regarding claim 17, Chen et al. and Wu et al. teach all of the limitations of claim 16 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), after forming an adhesion layer (92A) on the semiconductor die stack (50B/50A), further comprising:
forming a wetting layer (92B) on the semiconductor die stack (50B/50A); and
in the step of attaching the lid onto the flat top surface above the semiconductor die stack (50B/50A), the lid is thermally coupled to the primary semiconductor die (50B) further through the wetting layer (92B), and thermally coupled to the auxiliary semiconductor die (50A) further through the wetting layer (92B).
Regarding claim 18, Chen et al. and Wu et al. teach all of the limitations of claim 16 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), the primary semiconductor die (50B) and the auxiliary semiconductor die (50A) are bonded by hybrid bonding (see para [0065] wherein IC dies 50A or 50B is attached to the wafer 300 by hybrid bonding without the use of adhesive or solder, similarly ICs 50A and 50B in Fig, 33 bonded together).
Regarding claim 19, Chen et al. and Wu et al. teach all of the limitations of claim 16 from which this claim depends.
Chen et al. teaches wherein (Fig. 33), further comprising:
providing a substrate (110 called interposer, para [0085]); and
attaching the primary semiconductor die (50B) on a top surface of the substrate (110);
wherein the heat spreader (208) further comprises a plurality of lateral portions; and
wherein attaching the lid onto the flat top surface above the semiconductor die stack (50B/50A) further comprises:
attaching the plurality of lateral portions onto the top surface of the substrate (110) to support the heat spreader (208) on the substrate (110).
Response to Arguments
10. It has been acknowledged that the applicant amended claims 1, 4, 7, 11-12, 14-17, 19, per the response dated on 07/22/2026.
Applicant’s remarks in pages 10-12 have been considered, but they are moot because of new grounds of rejection in the current office action.
Conclusion
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
13. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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