Prosecution Insights
Last updated: April 19, 2026
Application No. 18/597,981

TWO-DIMENSIONAL (2D) MATERIAL FOR OXIDE SEMICONDUCTOR (OS) FERROELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICE

Final Rejection §102§103
Filed
Mar 07, 2024
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
2 (Final)
62%
Grant Probability
Moderate
3-4
OA Rounds
2y 8m
To Grant
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allow Rate
488 granted / 793 resolved
-6.5% vs TC avg
Strong +25% interview lift
Without
With
+25.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
52 currently pending
Career history
845
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
48.9%
+8.9% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 793 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings Examiner withdraws the drawing objections based upon Applicant’s statements on page 7 of the Remarks filed October 31, 2025. Specification Any and all specification corrections required in the parent application, 17/315,687, are required to be made in this continuation application. If Applicant has already incorporated said corrections, or no corrections were required, Applicant must make a statement to that effect to remove this objection. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Sharma et al. (US 2020/0388685 A1) (“Sharma”), in view of evidentiary reference Lee et al. (US 2021/0234015 A1) (“Lee”) as a MPEP 2131.01 evidentiary reference. Regarding claim 1, Sharma teaches at least in figure 12: An oxide semiconductor (OS) channel layer (1010) of a first doping type (¶¶ 0073, and 77, where 1010 is doped); A two-dimensional contacting layer (210) disposed over the OS channel layer (1010), Where in the 2D contacting layer is of a second doping type opposite to the first doping type (¶ 0073, where 210 can be a different conductivity (doping type) than 1010; ¶ 0077, where 210 and 1010 “may” have the same doping type. The use of “may” allows for “may not”, and “may” is not a “must”. Lee, teaches in figure 1A, a similar device to Sharma. Lee teaches in ¶ 0069 that the OS Channel layer and the 2D contacting layer can be the same doping type, different doping types, not doped, or some combination of the above. Therefore, Applicant’s assertion that the device of Sharma will not work as intended if 210 and 1010 are different doping types is directly contradicted by knowledge and skill of one of ordinary skill in the art as evidenced by Lee. Thus, Lee is being used to show what one of ordinary skill in the art knew before the effective filing date of the current application, as shown above, that one of ordinary skill in the art knew that 210 and 1010 could be different doping types and the device would still work. See also Sharma ¶ 0039, where more dopants can be added to 210 or 1010); a ferroelectric layer (315) disposed over the 2D contacting layer (210); a gate electrode (220) disposed over the ferroelectric layer (315); and a pair of source/drain regions (regions around 250) disposed over the 2D contacting layer (210), wherein the pair of source/drain regions (regions around 250) with a bottom surface (bottom of region around 250) on an upper lateral surface of the 2D contacting layer (top of 210). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0388685 A1) (“Sharma”), in view of Sharma et al. (US 2019/0267319 A1) (“Sharma II”). Regarding claim 1, Sharma teaches at least in figure 12: An oxide semiconductor (OS) channel layer (1010) of a first doping type (¶¶ 0073, and 77, where 1010 is doped); A two-dimensional contacting layer (210) disposed over the OS channel layer (1010), Where in the 2D contacting layer is of a second doping type opposite to the first doping type (¶ 0073, where 210 can be a different conductivity (doping type) than 1010; ¶ 0077, where 210 and 1010 “may” have the same doping type. The use of may allows for may not. Evidentiary reference Lee et al. (US 2021/0234015 A1) (“Lee”), used to retort Applicant’s arguments, teaches in figure 1A, a similar device to Sharma. Lee teaches in ¶ 0069 that the OS Channel layer and the 2D contacting layer can be the same doping type, different doping types, not doped, or some combination of the above. Therefore, Applicant’s assertion that the device of Sharma will not work as intended fi 210 and 1010 are different doping types is directly contradicted by knowledge and skill of one of ordinary skill in the art as evidenced by Lee. Examiner notes that the rejection is not currently based upon Lee. Rather, Lee is being used to show what one of ordinary skill in the art knew before the effective filing date of the current application. As shown above, one of ordinary skill in the art knew that 210 and 1010 could be different doping types and the device would still work. See also Sharma ¶ 0039, where more dopants can be added to 210 or 1010); a ferroelectric layer (315) disposed over the 2D contacting layer (210); a gate electrode (220) disposed over the ferroelectric layer (315); and a pair of source/drain regions (regions around 250) disposed over the 2D contacting layer (210), wherein the pair of source/drain regions (regions around 250) with a bottom surface (bottom of region around 250) on an upper lateral surface of the 2D contacting layer (top of 210). Regarding claim 19, Sharma teaches at least in figure 12: forming a stack of a gate electrode (220), a ferroelectric layer (315; ¶ 0114), and an oxide semiconductor (OS) channel layer (1010) one stacked over another (figure 12 shows they are stacked over one another), wherein the OS channel layer (1010) is formed with a first doping type (¶ 0073, where 1010 can have a first doping type); forming a two-dimensional (2D) contacting layer (210) on an upper lateral surface of the OS channel layer (1010), wherein the 2D contacting layer is formed of a second doping type opposite to the first doping type (¶ 0073, where 210 can be a different conductivity (doping type) than 1010; see also ¶ 0039, where more dopants can be added to 210 or 1010; See discussion of Lee in claim 1); forming a pair of source/drain regions (regions around 250) with a bottom surface (bottom of region around 250) on an upper lateral surface of the 2D contacting layer (top of 210). Sharma does not teach: forming a lower metal layer of an interconnect structure over a substrate; forming the stack over the lower metal layer; forming an upper metal layer of the interconnect structure over the stack. Sharma II teaches at least in figures 1-3: forming a lower metal layer (112/114 in 134) of an interconnect structure (112/114) over a substrate (136); forming the stack (102-110) over the lower metal layer (112/114 in 134); forming an upper metal layer (112/114 in 132) of the interconnect structure (112/114) over the stack (102-110). It would have been obvious to one of ordinary skill in the art to combine Sharma with Sharma II in order to allow for reconfigurable interconnect arrangements between the various components in the IC. ¶ 0014. Additionally, it would allow for the further miniaturization of semiconductor devices by stacking multiple transistors on top of each other; thereby reducing the area of the die and consequentially increasing the amount of IC/dies that can be formed on a standard wafer. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma, in view of Sharma II, Jeong et al. (US 2009/0294772 A1) (“Jeong”). Regarding claim 20, Sharma teaches at least in figure 12: wherein the 2D contacting layer (210) is formed with ending portions underlying the source/drain regions (ending portions of 210 underly region around 250) Sharma does not explicitly state: doped more heavily vertically throughout the 2D contacting layer than a middle portion between the source/drain regions. Jeong teaches at least in figure 2E: doped more heavily vertically throughout the 2D contacting layer than a middle portion between the source/drain regions (Jeong 18a-b under 20a-b, respectively, where the 2D contacting layer is more heavily doped than a middle portion; portion not under 20a-b). It would have been obvious to one of ordinary skill in the art to dope the portions of the 2D contacting layer with a greater concentration of doping than the middle of the 2D contacting layer. This is because one of ordinary skill in the art would want to create ohmic contacts between the portions of the 2D contacting layer underneath the source/drain regions and the source/drain region (e.g. contacts). Jeong ¶ 0031. By doping these portions of the 2D contacting layer one of ordinary skill in the art can ensure an ohmic contact between the 2D contacting layer and the source/drain region (e.g. contacts) will in fact be ohmic and not a Schottky contact which would change the characteristics of the transistor. Response to Arguments Applicant's arguments filed October 31, 2025 have been fully considered but they are not persuasive. Applicant asserts that Sharma does not teach the OS channel layer and the 2D contacting layer can be different doping types and it would break the device of Sharma. This argument is unpersuasive. As shown in the analysis of claim 1 above, Sharma teaches that 210 and 1010 may be the same doping type. Sharma does not teach they must be the same doping type. Further, evidentiary reference Lee teaches that one of ordinary skill in the art before the effective filing date of the current application would know these two layers could be the same or different doping types, or could be undoped, or could a combination. Therefore, Applicant’s arguments are not persuasive. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Mar 07, 2024
Application Filed
Jul 29, 2025
Non-Final Rejection — §102, §103
Oct 16, 2025
Applicant Interview (Telephonic)
Oct 16, 2025
Examiner Interview Summary
Oct 31, 2025
Response Filed
Dec 31, 2025
Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+25.4%)
2y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 793 resolved cases by this examiner. Grant probability derived from career allow rate.

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