Detailed Action
This office action is in response to the amendment filed March 5th, 2026. Claims 1-8 and 10-21 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed March 5th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 1-4, “Remarks”) that Choi and the other cited references fail to teach the limitations presented in amended Claims 1 and 15.
However, as seen below, Claim 1 is now rejected by a new interpretation of Choi. Claim 15 is now rejected by the combination of Choi and Tsai.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al. (KR 20210122000 A; hereinafter Choi).
Regarding Claim 1, Choi (annotated figs. 8-9) teaches a semiconductor device ([0015], semiconductor package, see fig. 1) comprising:
a first redistribution line ([0022], 55 below RBP1, referred to as first redistribution line, see annotated fig. 8) and a second redistribution line ([0022], 55 below DBP2, referred to as second redistribution line, see annotated fig. 8) over a semiconductor substrate ([0022], 51, see annotated fig. 8);
a first passivation layer ([0022], 52, see annotated fig. 9) over the first redistribution line (first redistribution line) and the second redistribution line (second redistribution line), wherein
the first passivation layer (52) extends along sidewalls of the first redistribution line (first redistribution line) and the second redistribution line (second redistribution line);
a second passivation layer ([0024], 59, see annotated fig. 9) over the first passivation layer (52);
a first under-bump metallurgy (UBM) structure ([0024]-[0025], RBP1, RPA1, 57, see annotated fig. 9) over the first redistribution line (first redistribution line), the first UBM structure (RBP1, RPA1, 57) extending through the first passivation layer (52) and the second passivation layer (59) and being electrically coupled to the first redistribution line (first redistribution line); and
a second UBM structure ([0046], DBP2, see annotated fig. 8) over the second redistribution line (second redistribution line), the second UBM structure (DBP2) extending at least partially through the second passivation layer (59), the second UBM structure (DBP2) being electrically isolated from the second redistribution line (second redistribution line) by the first passivation layer (52).
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Annotated Figure 8
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Annotated Figure 9
Note: Annotated figure 9 shows an enlarged view of region P1 (Choi, [0045]) from annotated figure 8. The figure has been corrected to appropriately show RBP1 in region R1 (Choi, [0025]).
Regarding Claim 2, Choi (annotated figs. 8-9) teaches the semiconductor device of claim 1, further comprising a protection layer ([0028], 60, see annotated fig. 8) over the second passivation layer (59), wherein the first UBM structure (RBP1, RPA1, 57) and the second UBM structure (DBP2) extend through the protection layer (60).
Regarding Claim 3, Choi (annotated figs. 8-9) teaches the semiconductor device of claim 2, wherein the protection layer (60) comprises a polymer material ([0028], may be formed from resin).
Regarding Claim 4, Choi (annotated figs. 8-9) teaches the semiconductor device of claim 3, wherein the first passivation layer (52) is a conformal layer (52 is applied to the whole device), wherein the second passivation layer (59) is a conformal layer (59 is applied to the whole device), and wherein the protection layer (60) has a planar top surface (see annotated fig. 8).
Regarding Claim 5, Choi (annotated figs. 8-9) teaches the semiconductor device of claim 1, wherein the first passivation layer (52) comprises an oxide ([0022], may be silicon oxide), and wherein the second passivation layer (59) comprises a nitride ([0024], 59 may include a layer of silicon nitride).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to Claim 1 above, and further in view of Stokes et al. (2017/0244380 A1; hereinafter Stokes).
Regarding Claim 6, Choi doesn’t teach the semiconductor device of claim 1, wherein a first width of the first UBM structure at a point level with a top surface of the second passivation layer and a second width of the second UBM structure at a point level with the top surface of the second passivation layer are less than 50 μm.
However, Stokes (figs. 2-3) teaches a first width ([0025], W4) of the first UBM structure ([0024], 42, 44A, 44B; see fig. 3) at a point level with a top surface of the second passivation layer ([0023], top of 38, see fig. 2) and a second width of the second UBM structure at a point level with the top surface of the second passivation layer are less than 50 μm ([0025], W4 ranges from 3.5 μm to 4.5 μm). Widths, however, will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating such widths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality of the claimed widths, and similar UBM structures are used for semiconductor devices in the art, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the appropriate width for a UBM structure. Additionally, the teachings of Stokes may be applied to the second UBM structure of Choi and thus teach a second width of the second UBM structure at a point level with the top surface of the second passivation layer is less than 50 μm.
Claims 15-16 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Tsai et al. (2018/0151528 A1; hereinafter Tsai).
Regarding Claim 15, Choi (annotated figs. 8-9) teaches a semiconductor device ([0015], semiconductor package, see fig. 1) comprising:
a first redistribution line ([0022], 55 below RBP1, referred to as first redistribution line, see annotated fig. 8) and a second redistribution line ([0022], 55 below DBP2, referred to as second redistribution line, see annotated fig. 8) over a semiconductor substrate ([0022], 51, see annotated fig. 8);
a first passivation layer ([0022], 52, see annotated fig. 9) over the first redistribution line (first redistribution line) and the second redistribution line (second redistribution line), wherein
a bottom surface of the first passivation layer is level with a bottom surface of the first redistribution line and a bottom surface of the second redistribution line;
a second passivation layer ([0024], 59, see annotated fig. 9) over the first passivation layer (52);
a first under-bump metallurgy (UBM) structure ([0024]-[0025], RBP1, RPA1, 57, see annotated fig. 9) over the first redistribution line (first redistribution line), the first UBM structure ([0024]-[0025], RBP1, RPA1, 57, see annotated fig. 9) extending through the first passivation layer (52) and the second passivation layer (59) and being electrically coupled to the first redistribution line (first redistribution line); and
a second UBM structure ([0046], DBP2, see annotated fig. 8) over the second redistribution line (second redistribution line), the second UBM structure (DBP2) extending at least partially through the second passivation layer (59), the first passivation layer (52) separating the second UBM structure (DBP2) from the second redistribution line (second redistribution line).
Choi doesn’t teach that a bottom surface of the first passivation layer is level with a bottom surface of the first redistribution line and a bottom surface of the second redistribution line.
However, Tsai (annotated fig. 4) teaches a bottom surface of the first passivation layer ([0017], bottom surface of topmost layer 54, referred to as first passivation layer) is level with a bottom surface of the first redistribution line ([0017], bottom surface of a first 42, referred to as first redistribution line) and a bottom surface of the second redistribution line ([0017], bottom surface of a second 42, referred to as second redistribution line). Tsai also teaches that the redistribution lines may be formed using a single or dual damascene process within the passivation layer ([0019]) while still forming a functional redistribution lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Choi and Tsai to enable the formation of redistribution lines step of Choi to be performed according to the teachings of Tsai because one of ordinary skill in the art would have been motivated to look to alternative suitable methods of performing the formation of redistribution lines step disclosed in Choi and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
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Annotated Figure 4
Regarding Claim 16, Choi (annotated figs. 8-9) teaches the semiconductor device of claim 15, wherein the first passivation layer (52) extends along a sidewall of the first redistribution line (sidewall of first redistribution line, see annotated fig. 9).
Regarding Claim 21, Choi (annotated figs. 8-9) teaches the semiconductor device of claim 15, wherein the first passivation layer (52) contacts the first redistribution line (first redistribution line) and the second redistribution line (second redistribution line).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Choi and Tsai as applied to Claim 16, above, and further in view of Cheng et al. (2018/0151525 A1; hereinafter Cheng).
Regarding Claim 17, Choi doesn’t teach the semiconductor device of claim 16, wherein the second passivation layer extends along the sidewall of the first redistribution line.
However, Cheng (fig. 3D) teaches the second passivation layer ([0023], 364) extends along the sidewall of the first redistribution line ([0023], 342’). Cheng teaches the passivation structure provided helps control the shape of the RDL ([0023]) which can result in improved step coverage of a subsequent protective layer ([0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Choi to include the second passivation layer structure of Cheng to provide improved step coverage of a subsequent protective layer.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Choi and Tsai as applied to Claim 15, and further in view of Jain (2019/0206730 A1; hereinafter Jain).
Regarding Claim 20, Choi (annotated figs. 8-9) teaches the semiconductor device of claim 15, further comprising a protection layer ([0028], 60, see annotated fig. 8) over the second passivation layer (59b), the protection layer (60) comprising a polymer material ([0028], may be formed from resin). ). Choi doesn’t teach the first UBM structure and the second UBM structure extends over a top surface of the protection layer.
However, Jain (fig. 2B) teaches the first UBM structure ([0029], 208) [] extends over a top surface of the protection layer ([0030], 214) ) while still properly functioning as a UBM for coupling to other devices. One of ordinary skill in the art could have substituted the UBM structure of Jain for the UBM structure of Choi and yielded the predictable results of a functional UBM for coupling to other devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the UBM structure of Jain for the UBM structure of Choi, since simple substitution of UBM structures for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Additionally, the teachings of Jain may be applied to the second UBM structure of Choi and thus teach the second UBM structure comprises a second pad portion extending along the top surface of the protection layer.
Allowable Subject Matter
Claims 8 and 10-14 are allowed.
The following is an examiner’s statement of reasons for allowance. None of the references cited, either singly or in combination, teach or render obvious the limitations presented in Claim 8 wherein “the plurality of conductive traces comprises a first conductive trace and a second conductive trace, wherein the second UBM structure comprises a second via portion extending between the first conductive trace and the second conductive trace, and wherein a bottom surface of the second via portion is below top surfaces of the first conductive trace and the second conductive trace”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Additionally, Claims 7 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. None of the references cited, either singly or in combination, teach or render obvious the limitations presented in Claim 7 wherein “the first UBM structure comprises a first via portion extending through the first passivation layer and the second passivation layer, the first via portion having a first height between a bottom surface of the first UBM structure and a point level with a top surface of the second passivation layer, wherein the second UBM structure comprises a second via portion extending at least partially through the second passivation layer, the second via portion having a second height between a bottom surface of the second UBM structure and a point level with the top surface of the second passivation layer, and wherein the first height is greater than the second height by 1.0 μm to 2.5 μm” and in Claim 18 wherein “further comprising conductive traces adjacent the second redistribution line , wherein the second UBM structure extends between the second redistribution line and a first trace of the conductive traces.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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