CTNF 18/598,580 CTNF 89876 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-35 Claim 20 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 20 of copending Application No. 19/286,967 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because application claim 20 is anticipated by claim 20 of the copending Application, and it is not patentably distinct from claim 20 of the copending Application. See the table as shown below: Under Examination Claims Claims of copending Application 20. A semiconductor device comprising: a semiconductor region; a gate structure on the semiconductor region; an insulating layer of a dielectric material contacting a top of the gate structure and extending across a full width of the top of the gate structure; a first gate spacer and a second gate spacer; and an interlayer dielectric layer along sides of the first and second gate spacers, wherein: the gate structure has a lower portion and an upper portion, the lower portion extending vertically between the first and second gate spacers and having a first width, and the upper portion extending vertically from the lower portion to the insulating layer, and having a second width that is greater than the first width, the first gate spacer has a first inner sidewall that faces a first side of the lower portion of the gate structure, and the second gate spacer has a second inner sidewall that faces a second side of the lower portion of the gate structure, the first inner sidewall being spaced apart from the second inner sidewall by a first distance, and the insulating layer has a width that is greater than the first distance. Anticipated by Claim 1 of copending Application: 20. A transistor comprising: a gate structure including a gate conductive structure and a gate dielectric layer at first and second sides of the gate conductive structure; an insulating layer of a dielectric material extending across and contacting an uppermost surface of the gate structure and contacting an uppermost surface of the gate dielectric at the first and second sides of the gate conductive structure; a first gate spacer and a second gate spacer; and an interlayer dielectric layer along sides of the first and second gate spacers and along sides of the insulating layer, wherein: the gate structure has a lower portion and an upper portion, the lower portion being between the first and second gate spacers, and the upper portion extending from the lower portion to the insulating layer, and being wider than the lower portion, the first gate spacer has a first inner sidewall that faces a first side of the lower portion of the gate structure, and the second gate spacer has a second inner sidewall that faces a second side of the lower portion of the gate structure, the first inner sidewall being spaced apart from the second inner sidewall by a first distance, and the insulating layer has a width that is greater than the first distance . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1, 11-15, and 18-19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Park et al. (U.S. 2015/0187946 A1, hereinafter refer to Park) . Regarding Claim 1: Park discloses a method of fabricating a semiconductor device (see Park, Figs.2, 3A, 12-13, and 24-31 as shown below and ¶ [0003]), the method comprising: PNG media_image1.png 403 843 media_image1.png Greyscale PNG media_image2.png 506 866 media_image2.png Greyscale PNG media_image3.png 316 848 media_image3.png Greyscale PNG media_image4.png 289 901 media_image4.png Greyscale forming a dummy gate ( 111/112 ) and gate spacers ( 140 ) on a semiconductor region of a substrate ( 100 ) (see park, Fig.24 as shown above and ¶ [0249]); forming an interlayer dielectric layer ( 182 ) along sides of the gate spacers ( 140 ) (see park, Fig.24 as shown above and ¶ [0253]); forming a trench ( 145 ) having a lower portion and an upper portion, the upper portion of the trench being wider than the lower portion of the trench (see park, Fig.27 as shown above and ¶ [0276]]), forming the trench ( 145 ) including: removing a part of the gate spacers ( 140 ) (see park, Fig.27 as shown above and ¶ [0276]), and removing the dummy gate ( 111/112 ) (see park, Fig.27 as shown above and ¶ [0276]); and forming a gate structure ( 110/120/130 ) in the trench ( 145 ) (see park, Figs.28-29 as shown above), wherein: the gate structure ( 110/120/130 ) has a lower portion and an upper portion, the upper portion of the gate structure being in the upper portion of the trench ( 145 ), the lower portion of the gate structure being in the lower portion of the trench ( 145 ), and the upper portion of the gate structure being wider than the lower portion of the gate structure (see park, Figs.28-29 as shown above), a first one of the gate spacers ( 140a ) has a first inner sidewall that faces a first side of the lower portion of the gate structure ( 110/120/130 ), and a second one of the gate spacers ( 140a ) has a second inner sidewall that faces a second side of the lower portion of the gate structure ( 110/120/130 ), the first inner sidewall being spaced apart from the second inner sidewall by a first distance ( W1/L1 ) (see park, Figs.2-3A and 28-29 as shown above), and wherein the upper portion of the gate structure ( W3/L3 ) has a width that is greater than the first distance ( W1/L1 ) (see park, Figs.2-3A and 28-29 as shown above). Regarding Claim 11: Park discloses a method of fabricating a semiconductor device as set forth in claim 1 as above. Park further teaches wherein: forming the trench ( 145 ) includes making upper portions of gate spacers ( 140 ) narrower (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), and sides of the upper portion of the trench ( 145 ) are defined by sidewalls of upper portions of the gate spacers ( 140 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above). Regarding Claim 12: Park discloses a method of fabricating a semiconductor device as set forth in claim 11 as above. Park further teaches wherein: forming the trench ( 145 ) includes performing at least one etch operation to remove the part of the gate spacers ( 140 ) and the dummy gate ( 111/112 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), and the gate spacers ( 140 ) are etched so that the sidewalls of the upper portion of the trench ( 145 ) are aligned with a point between inner sides and outer sides of the gate spacers ( 140 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above). Regarding Claim 13: Park discloses a method of fabricating a semiconductor device as set forth in claim 1 as above. Park further teaches wherein: the gate structure ( 110/120/130 ) includes a filling conductor ( 130 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), the filling conductor ( 130 ) is formed to have a lower portion and an upper portion (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), the upper portion of the filling conductor ( 130 ) is in the upper portion of the trench ( 145 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), the lower portion of the filling conductor ( 130 ) is in the lower portion of the trench (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), and the upper portion of the filling conductor ( 130 ) is wider than the lower portion of the filling conductor ( 130 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above). Regarding Claim 14: Park discloses a method of fabricating a semiconductor device as set forth in claim 1 as above. Park further teaches wherein forming the gate structure ( 110/120/130 ) includes: forming a gate dielectric layer ( 110 ), the gate dielectric layer ( 110 ) being formed to have a substantially uniform first thickness (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above); forming a work function layer ( 120 ) on the gate dielectric layer ( 110 ), the work function layer ( 120 ) being formed to have a substantially uniform second thickness (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above); and forming a filling conductor ( 130 ) on the work function layer ( 120 ), the filling conductor ( 130 ) being formed to fill a remaining part of the trench ( 145 ) not occupied by the gate dielectric layer ( 110 ) and the work function layer ( 120 ), and having a greater electrical conductivity than the work function layer (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above). Regarding Claim 15: Park discloses a semiconductor device (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above and ¶ [0003]) comprising: a semiconductor region having a channel region therein (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above); a gate structure ( 110/120/130 ) adjacent to the channel region (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above); a first gate spacer ( 140 ) at a first side of the gate structure ( 110/120/130 ) and a second gate spacer ( 140 ) at a second side of the gate structure ( 110/120/130 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above); and an interlayer dielectric layer ( 182 ) along sides of the first and second gate spacers ( 140 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), wherein: the gate structure ( 110/120/130 ) has a lower portion and an upper portion, a width of the upper portion of the gate structure ( 110/120/130 ) being different from a width of the lower portion of the gate structure ( 110/120/130 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), the first gate spacer ( 140a ) has a first inner sidewall that faces a first side of the lower portion of the gate structure ( 110/120/130 ), and the second gate spacer ( 140a ) has a second inner sidewall that faces a second side of the lower portion of the gate structure ( 110/120/130 ), the first inner sidewall being spaced apart from the second inner sidewall by a first distance ( W1/L1 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), and the upper portion of the gate structure ( 110/120/130 ) has a width ( W3/L3 ) that is greater than the first distance ( W1/L1 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above). Regarding Claim 18: Park discloses a semiconductor device as set forth in claim 15 as above. Park further teaches wherein: the first and second gate spacers ( 140a/140b ) each have a wider bottom portion ( 140a ) and a narrower top portion ( 140b ) with a substantially horizontal step between the bottom portion and the top portion (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), and outer sidewalls of the upper portion of the gate structure ( 110/120/130 ) contact inner sidewalls of the top portions of the first and second gate spacers ( 140a/140b ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above). Regarding Claim 19: Park discloses a semiconductor device as set forth in claim 15 as above. Park further teaches wherein an insulating layer ( 150 ) on top of the gate structure ( 110/120/130 ) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), wherein the first and second gate spacers ( 140a/140b ) have a height that is at least ⅓ of an overall distance from a bottom of the first and second gate spacers ( 140a/140b ) to a top of the insulating layer ( 150 ) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-22-aia AIA Claim (s) 2-10 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2015/0187946 A1, hereinafter refer to Park) as applied to claim s 1 and 15 above, and further in view of Kuo et al. (U.S. 2021/0234021 A1, hereinafter refer to Kuo) . Regarding Claim 2: Park discloses a method of fabricating a semiconductor device as applied to claim 1 above. Park is silent upon explicitly disclosing wherein: forming the trench includes removing a part of the interlayer dielectric layer, sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and a minimum separation of the sidewalls is greater than a distance between outer sides of the gate spacers. For support see Kuo, which teaches wherein: forming the trench includes removing a part of the interlayer dielectric layer ( 810A ) (see Kuo, Fig.8 as shown below and ¶ [0018]), sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer ( 810A ) (see Kuo, Fig.8 as shown below and ¶ [0018]), and a minimum separation of the sidewalls is greater than a distance between outer sides of the gate spacers ( 810B ) (see Kuo, Fig.8 as shown below and ¶ [0018]). PNG media_image5.png 459 706 media_image5.png Greyscale PNG media_image6.png 457 693 media_image6.png Greyscale PNG media_image7.png 457 708 media_image7.png Greyscale Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Kuo to enable forming the trench includes removing a part of the interlayer dielectric layer, sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and a minimum separation of the sidewalls is greater than a distance between outer sides of the gate spacers as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed. Regarding Claim 3: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 2 as above. The combination of Park and Kuo further teaches wherein: forming the trench includes performing at least one etch operation to remove the part of the interlayer dielectric layer ( 810A ), the part of the gate spacers ( 810B ), and the dummy gate ( 307 ) (see Kuo, Fig.8 as shown above and ¶ [0018]), and the part of the interlayer dielectric layer ( 810A ) is etched so that the upper portion of the trench is wider than the distance between outer sides of the gate spacers ( 810B ) (see Kuo, Fig.8 as shown above and ¶ [0018]). Regarding Claim 4: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 2 as above. The combination of Park and Kuo further teaches wherein forming the trench includes forming the sidewalls to have an angle D1 relative to a major plane of a surface of the substrate ( 101 ) that ranges from 90 degrees to 120 degrees (see Kuo, Fig.8 as shown above). Regarding Claim 5: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 4 as above. The combination of Park and Kuo further teaches wherein the upper portion of the gate structure ( 605/607 ) is formed to have sides that have the angle D1 relative to the major plane of the surface of the substrate ( 101 ) (see Kuo, Fig.8 as shown above). Regarding Claim 6: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 5 as above. The combination of Park and Kuo further teaches wherein D1 is greater than 90 degrees (see Kuo, Fig.8 as shown above). Regarding Claim 7: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 2 as above. The combination of Park and Kuo further teaches wherein forming an insulating layer ( 150 ) on top of the gate structure ( 110/120/130 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above), wherein the gate spacers ( 140a and 140b ) have a height that is at least ⅓ of an overall distance from a bottom of the gate spacers ( 140a and 140b ) to a top of the insulating layer ( 150 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above). Regarding Claim 8: Park discloses a method of fabricating a semiconductor device as applied to claim 1 above. Park is silent upon explicitly disclosing wherein: forming the trench includes removing a part of the interlayer dielectric layer, sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and a minimum separation of the sidewalls is approximately the same as a distance between outer sides of the gate spacers. For support see Kuo, which teaches wherein: forming the trench includes removing a part of the interlayer dielectric layer ( 710A ) (see Kuo, Fig.7 as shown above and ¶ [0018]), sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer ( 710A ) (see Kuo, Fig.7 as shown above and ¶ [0018]), and a minimum separation of the sidewalls is approximately the same as a distance between outer sides of the gate spacers ( 710B ) (see Kuo, Fig.7 as shown above and ¶ [0018]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Kuo to enable forming the trench includes removing a part of the interlayer dielectric layer, sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and a minimum separation of the sidewalls is approximately the same as a distance between outer sides of the gate spacers as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed. Regarding Claim 9: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 8 as above. The combination of Park and Kuo further teaches wherein: forming the trench includes performing at least one etch operation to remove the part of the interlayer dielectric layer ( 710A/810A ), the part of the gate spacers ( 710B/810B ), and the dummy gate ( 307 ) (see Kuo, Fig.8 as shown above and ¶ [0018]), and the part of the interlayer dielectric layer ( 710A/810A ) is etched so that the sidewalls of the interlayer dielectric layer ( 710A/810A ) in the upper portion of the trench are substantially aligned with outer sides of the gate spacers ( 810B ) (see Kuo, Fig.8 as shown above and ¶ [0018]). Regarding Claim 10: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 8 as above. The combination of Park and Kuo further teaches wherein forming an insulating layer ( 150 ) on top of the gate structure ( 110/120/130 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above), wherein the gate spacers ( 140a and 140b ) have a height that is at least ⅓ of an overall distance from a bottom of the gate spacers ( 140 ) to a top of the insulating layer ( 150 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above). Regarding Claim 16: Park discloses a semiconductor device as applied to claim 15 above. Park is silent upon explicitly disclosing wherein the upper portion of the gate structure has a width that is greater than a distance between outer sidewalls of the first and second gate spacers. For support see Kuo, which teaches wherein the upper portion of the gate structure ( 605/607 ) has a width that is greater than a distance between outer sidewalls of the first and second gate spacers ( 810B ) (see Kuo, Fig.8 as shown above and ¶ [0018]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Kuo to enable the upper portion of the gate structure to have a width that is greater than a distance between outer sidewalls of the first and second gate spacers as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed. Regarding Claim 17: Park discloses a semiconductor device as applied to claim 15 above. Park is silent upon explicitly disclosing wherein the upper portion of the gate structure has a width that is approximately the same as a distance between outer sides of the first and second gate spacers. For support see Kuo, which teaches wherein the upper portion of the gate structure ( 605/607 ) has a width that is approximately the same as a distance between outer sides of the first and second gate spacers ( 710B ) (see Kuo, Fig.7 as shown above and ¶ [0018]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Kuo to enable the upper portion of the gate structure to have a width that is approximately the same as a distance between outer sides of the first and second gate spacers as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed . 07-21-aia AIA Claim (s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2015/0187946 A1, hereinafter refer to Park) in view of Kuo et al. (U.S. 2021/0234021 A1, hereinafter refer to Kuo) . Regarding Claim 20: Park discloses a semiconductor device (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above and ¶ [0003]) comprising: a semiconductor region (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above); a gate structure ( 110/120/130 ) on the semiconductor region (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above); an insulating layer of a dielectric material ( 150 ) contacting a top of the gate structure ( 110/120/130 ) and extending across a full width of the top of the gate structure ( 110/120/130 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above); a first gate spacer ( 140 ) and a second gate spacer ( 140 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above); and an interlayer dielectric layer ( 182 ) along sides of the first and second gate spacers ( 140 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above), wherein: the gate structure ( 110/120/130 ) has a lower portion and an upper portion (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above), the upper portion extending vertically from the lower portion to the insulating layer ( 150 ), and having a second width ( W3/L3 ) that is greater than the first width ( W1/L1 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above), the first gate spacer ( 140 ) has a first inner sidewall that faces a first side of the lower portion of the gate structure ( 110/120/130 ), and the second gate spacer ( 140 ) has a second inner sidewall that faces a second side of the lower portion of the gate structure ( 110/120/130 ), the first inner sidewall being spaced apart from the second inner sidewall by a first distance ( W1/L1 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above), and the insulating layer ( 150 ) has a width ( W3/L3 ) that is greater than the first distance ( W1/L1 ) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above). Park is silent upon explicitly disclosing wherein the lower portion extending vertically between the first and second gate spacers and having a first width. For support see Kuo, which teaches wherein the lower portion extending vertically between the first and second gate spacers ( 710B/810B ) and having a first width (see Kuo, Fig.7 as shown above and ¶ [0018]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Kuo to enable the lower portion to be extend vertically between the first and second gate spacers and having a first width as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BITEW A DINKE/Primary Examiner, Art Unit 2812 Application/Control Number: 18/598,580 Page 2 Art Unit: 2812 Application/Control Number: 18/598,580 Page 3 Art Unit: 2812 Application/Control Number: 18/598,580 Page 4 Art Unit: 2812 Application/Control Number: 18/598,580 Page 5 Art Unit: 2812 Application/Control Number: 18/598,580 Page 6 Art Unit: 2812 Application/Control Number: 18/598,580 Page 7 Art Unit: 2812 Application/Control Number: 18/598,580 Page 8 Art Unit: 2812 Application/Control Number: 18/598,580 Page 9 Art Unit: 2812 Application/Control Number: 18/598,580 Page 10 Art Unit: 2812 Application/Control Number: 18/598,580 Page 11 Art Unit: 2812 Application/Control Number: 18/598,580 Page 12 Art Unit: 2812 Application/Control Number: 18/598,580 Page 13 Art Unit: 2812 Application/Control Number: 18/598,580 Page 15 Art Unit: 2812 Application/Control Number: 18/598,580 Page 16 Art Unit: 2812 Application/Control Number: 18/598,580 Page 17 Art Unit: 2812 Application/Control Number: 18/598,580 Page 18 Art Unit: 2812 Application/Control Number: 18/598,580 Page 19 Art Unit: 2812 Application/Control Number: 18/598,580 Page 20 Art Unit: 2812 Application/Control Number: 18/598,580 Page 21 Art Unit: 2812 Application/Control Number: 18/598,580 Page 22 Art Unit: 2812 Application/Control Number: 18/598,580 Page 23 Art Unit: 2812
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