Prosecution Insights
Last updated: October 01, 2026
Application No. 18/598,866

MOSFETS WITH IMPLANTED CHARGE COMPENSATION REGIONS

Non-Final OA §102§103
Filed
Mar 07, 2024
Priority
May 15, 2023 — provisional 63/466,479
Examiner
MEHTA, RATISHA
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
578 granted / 645 resolved
+21.6% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
36 currently pending
Career history
671
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
47.4%
+7.4% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
12.7%
-27.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 645 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I in the reply filed on 6/22/2026 is acknowledged. Claims 17-31 are canceled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/22/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20190140049; hereinafter Zhang). Regarding claim 1, Fig 6h of Zhang discloses a semiconductor device comprising: a semiconductor layer having (102; Fig 6h; ¶ [0049]) a first conductivity type (N-type; ¶ [0049]); a well region (112; Fig 6h; ¶ [0051]) in the semiconductor layer (102; Fig 6h; ¶ [0049]), the well region (112; Fig 6h; ¶ [0051]) having a second conductivity type (P-type; ¶ [0051]) opposite the first conductivity type (N-type; ¶ [0049]); a source region (113; Fig 6h; ¶ [0051]) in the well region (112; Fig 6h; ¶ [0051]), wherein the source region has the first conductivity type (N-type; ¶ [0051]), wherein the source region (113; Fig 6h; ¶ [0051]) is adjacent a channel region (¶ [0052]) in the well region; and an implanted charge compensation region (111/110a/120a; Fig 6h; ¶ [0050]) in the semiconductor layer (102; Fig 6h; ¶ [0049]) beneath (Fig 6h) the well region (112; Fig 6h; ¶ [0051]). Regarding claim 2, Fig 6h of Zhang discloses the charge compensation region (111/110a; Fig 6h; ¶ [0050]) increases a voltage blocking capability of the semiconductor device (¶ [0059]). Regarding claim 3, Fig 6h of Zhang discloses a gate insulating layer (115; Fig 6h; ¶ [0052]) on the semiconductor layer (102; Fig 6h; ¶ [0049]) above the channel region (¶ [0052]), a gate contact (116; Fig 6h; ¶ [0049]) on the gate insulating layer (115; Fig 6h; ¶ [0052]) and a first contact (118; Fig 6h; ¶ [0054]) on the source region (113; Fig 6h; ¶ [0051]). Regarding claim 4, Fig 6h of Zhang discloses a substrate (101; Fig 6h; ¶ [0049]) having the first conductivity type (N-type; ¶ [0049]), wherein the semiconductor layer (102; Fig 6h; ¶ [0049]) is on the substrate (101; Fig 6h; ¶ [0049]) and a second contact (108; Fig 6h; ¶ [0054]) on the substrate (101; Fig 6h; ¶ [0049]). Regarding claim 11, Fig 6h of Zhang discloses the charge compensation region (111/110a; Fig 6h; ¶ [0050]) decreases an electric field strength in the semiconductor layer in an area around the charge compensation region during a voltage blocking operation of the device. (¶ [0067]) Regarding claim 12, Fig 6h of Zhang discloses a doped well contact region (114; Fig 6h; ¶ [0051]) in the semiconductor layer (102; Fig 6h; ¶ [0049]) adjacent the source region (113; Fig 6h; ¶ [0051]), wherein the well contact region (114; Fig 6h; ¶ [0051]) has the second conductivity type (¶ [0051]) and contacts the well region (112; Fig 6h; ¶ [0051]), wherein the charge compensation region (111/110a; Fig 6h; ¶ [0050]) is at least partially provided beneath the well contact region. Regarding claim 13, Fig 6h of Zhang discloses a doped well contact region (104; Fig 6h; ¶ [0053]) in the semiconductor layer (102; Fig 6h; ¶ [0049]) adjacent the source region (113; Fig 6h; ¶ [0051]), wherein the well contact region (104; Fig 6h; ¶ [0051]) has the second conductivity type (¶ [0051]) and contacts the well region (112; Fig 6h; ¶ [0051]), wherein the charge compensation region (111/110a; Fig 6h; ¶ [0050]) is not provided directly beneath the well contact region. Regarding claim 14, Fig 6h of Zhang discloses the charge compensation region (111/110a (left side); Fig 6h; ¶ [0050]) is spaced apart from the well region (112 (right side); Fig 6h; ¶ [0051]) in a vertical direction. Regarding claim 15, Fig 6h of Zhang discloses a vertical conduction region (104; Fig 6h; ¶ [0053]) adjacent the well region (112; Fig 6h; ¶ [0051]), wherein the charge compensation region (111/110a/120a; Fig 6h; ¶ [0050]) is formed beneath a lower corner of the well region near the vertical conduction region. (Fig 6h) Regarding claim 16, Fig 6h of Zhang discloses the charge compensation region (111/110a/120a; Fig 6h; ¶ [0050]) extends past the lower corner of the well region and into the vertical conduction region. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20190140049; hereinafter Zhang) as applied to claim 1 and further in view of Wu et al (US 2021/0376075; hereinafter Wu). Regarding claim 5, Zhang does not expressly disclose the charge compensation region (111/110a; Fig 6h; ¶ [0050]) comprises non-activated implanted dopant ions. In the same field of endeavor, Fig 12 of Wu discloses a charge compensation/trapping layer (20; Fig 12; ¶ [0044]) can comprise non-electrical dopants such as argon (¶ [0044]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a charge compensation/trapping layer can comprise non-electrical dopants such as argon for the purpose of using non-electrical dopants in suppressing growth in the charge-trapping/compensation layer in subsequent high temperature processing steps (¶ [0044]). Claim(s) 6, 9, 32-38, 41-45 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20190140049; hereinafter Zhang) and further in view of Schulze et al (US 2020/0381253; hereinafter Schulze). Regarding claim 6, Fig 6h of Zhang does not expressly disclose the semiconductor layer comprises silicon carbide and wherein the charge compensation region comprises hydrogen, aluminum or nitrogen dopant ions. In the same field of endeavor, Fig 7H of Schulze discloses a semiconductor layer (700; Fig 7H; ¶ [0125]) comprises silicon carbide (¶ [0125]) and a charge compensation region (281; Fig 7H; ¶ [0132]) comprises aluminum ions (¶ [0048]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective date of the invention such that the semiconductor layer comprises silicon carbide and wherein the charge compensation region comprises hydrogen, aluminum or nitrogen dopant ions as taught by Schulze for in order to achieve an attractive super junction performance (¶ [0048]). Regarding claim 9, Fig 6h of Zhang discloses the charge compensation region (111/110a; Fig 6h; ¶ [0050]) comprises dopant ions that form deep level traps in the semiconductor layer (¶ [0067]). However Zhang does not expressly disclose the semiconductor layer comprises silicon carbide. In the same field of endeavor, Fig 7H of Schulze discloses a semiconductor layer (700; Fig 7H; ¶ [0125]) comprises silicon carbide (¶ [0125]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective date of the invention such that the semiconductor layer comprises silicon carbide as taught by Schulze for in order to achieve an attractive super junction performance (¶ [0048]). Regarding claim 32, Fig 6h of Zhang discloses a semiconductor layer having (102; Fig 6h; ¶ [0049]) a first conductivity type (N-type; ¶ [0049]); a well region (112; Fig 6h; ¶ [0051]) in the semiconductor layer (102; Fig 6h; ¶ [0049]), the well region (112; Fig 6h; ¶ [0051]) having a second conductivity type (P-type; ¶ [0051]) opposite the first conductivity type (N-type; ¶ [0049]); a source region (113; Fig 6h; ¶ [0051]) in the well region (112; Fig 6h; ¶ [0051]), wherein the source region has the first conductivity type (N-type; ¶ [0051]), wherein the source region (113; Fig 6h; ¶ [0051]) is adjacent a channel region (¶ [0052]) in the well region; and an implanted charge compensation region (111/110a/120a; Fig 6h; ¶ [0050]) in the semiconductor layer (102; Fig 6h; ¶ [0049]) beneath (Fig 6h) the well region (112; Fig 6h; ¶ [0051]), wherein the charge compensation region form deep level traps in the semiconductor layer. (¶ [0067]). However Zhang does not expressly disclose the semiconductor layer comprises silicon carbide and the charge compensation region comprises inert ions, non-activated implanted dopant ions and/or dopant ions that form deep level traps in the semiconductor layer. In the same field of endeavor, Fig 7H of Schulze discloses a semiconductor layer (700; Fig 7H; ¶ [0125]) comprises silicon carbide (¶ [0125]) and a charge compensation region (281; Fig 7H; ¶ [0132]) comprises aluminum ions (¶ [0048]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective date of the invention such that the semiconductor layer comprises silicon carbide and wherein the charge compensation region comprises hydrogen, aluminum or nitrogen dopant ions as taught by Schulze for in order to achieve an attractive super junction performance (¶ [0048]). Regarding claim 33, Fig 6h of Zhang discloses a doped well contact region (114; Fig 6h; ¶ [0051]) in the semiconductor layer (102; Fig 6h; ¶ [0049]) adjacent the source region (113; Fig 6h; ¶ [0051]), wherein the well contact region (114; Fig 6h; ¶ [0051]) has the second conductivity type (¶ [0051]) and contacts the well region (112; Fig 6h; ¶ [0051]), wherein the charge compensation region (111/110a; Fig 6h; ¶ [0050]) is at least partially provided beneath the well contact region. Regarding claim 34, Fig 6h of Zhang discloses a doped well contact region (104; Fig 6h; ¶ [0053]) in the semiconductor layer (102; Fig 6h; ¶ [0049]) adjacent the source region (113; Fig 6h; ¶ [0051]), wherein the well contact region (104; Fig 6h; ¶ [0051]) has the second conductivity type (¶ [0051]) and contacts the well region (112; Fig 6h; ¶ [0051]), wherein the charge compensation region (111/110a; Fig 6h; ¶ [0050]) is not provided directly beneath the well contact region. Regarding claim 35, Fig 6h of Zhang discloses the charge compensation region (111/110a (left side); Fig 6h; ¶ [0050]) is spaced apart from the well region (112 (right side); Fig 6h; ¶ [0051]). Regarding claim 36, Fig 6h of Zhang discloses a vertical conduction region (104; Fig 6h; ¶ [0053]) adjacent the well region (112; Fig 6h; ¶ [0051]), wherein the charge compensation region (111/110a/120a; Fig 6h; ¶ [0050]) is formed beneath a lower corner of the well region near the vertical conduction region. (Fig 6h) Regarding claim 37, Fig 6h of Zhang discloses the charge compensation region (111/110a/120a; Fig 6h; ¶ [0050]) extends past the lower corner of the well region and into the vertical conduction region. Regarding claim 38, Fig 6h of Zhang does not expressly disclose non-activated implanted dopant ions comprises hydrogen, aluminum or nitrogen dopant ions. In the same field of endeavor, Fig 7H of Schulze discloses a charge compensation region (281; Fig 7H; ¶ [0132]) comprises aluminum ions (¶ [0048]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective date of the invention such that the semiconductor layer comprises silicon carbide and wherein the charge compensation region comprises hydrogen, aluminum or nitrogen dopant ions as taught by Schulze for in order to achieve an attractive super junction performance (¶ [0048]). Regarding claim 41, Fig 6h of Zhang discloses the charge compensation region (111/110a; Fig 6h; ¶ [0050]) increases a voltage blocking capability of the semiconductor device (¶ [0059]). Regarding claim 42, Fig 6h of Zhang discloses the charge compensation region (111/110a; Fig 6h; ¶ [0050]) decreases an electric field strength in the semiconductor layer in an area around the charge compensation region during a voltage blocking operation of the device. (¶ [0067]) Regarding claim 43, Fig 6h of Zhang discloses a semiconductor layer having (102; Fig 6h; ¶ [0049]) a first conductivity type (N-type; ¶ [0049]); a well region (112; Fig 6h; ¶ [0051]) in the semiconductor layer (102; Fig 6h; ¶ [0049]), the well region (112; Fig 6h; ¶ [0051]) having a second conductivity type (P-type; ¶ [0051]) opposite the first conductivity type (N-type; ¶ [0049]); a source region (113; Fig 6h; ¶ [0051]) in the well region (112; Fig 6h; ¶ [0051]), wherein the source region has the first conductivity type (N-type; ¶ [0051]), wherein the source region (113; Fig 6h; ¶ [0051]) is adjacent a channel region (¶ [0052]) in the well region; and an implanted charge compensation region (111/110a/120a; Fig 6h; ¶ [0050]) in the semiconductor layer (102; Fig 6h; ¶ [0049]) beneath (Fig 6h) the well region (112; Fig 6h; ¶ [0051]); a doped well contact region (114; Fig 6h; ¶ [0051]) in the semiconductor layer (102; Fig 6h; ¶ [0049]) adjacent the source region (113; Fig 6h; ¶ [0051]), wherein the well contact region (114; Fig 6h; ¶ [0051]) has the second conductivity type (¶ [0051]) and contacts the well region (112; Fig 6h; ¶ [0051]), wherein the charge compensation region (111/110a; Fig 6h; ¶ [0050]) is at least partially provided beneath the well contact region. However Zhang does not expressly disclose the semiconductor layer comprises silicon carbide. In the same field of endeavor, Fig 7H of Schulze discloses a semiconductor layer (700; Fig 7H; ¶ [0125]) comprises silicon carbide (¶ [0125]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective date of the invention such that the semiconductor layer comprises silicon carbide as taught by Schulze for in order to achieve an attractive super junction performance (¶ [0048]). Regarding claim 44, Zhang does not expressly disclose the charge compensation region comprises inert ions, non-activated implanted dopant ions and/or dopant ions that form deep level traps in the semiconductor layer. In the same field of endeavor, Fig 7H of Schulze discloses a charge compensation region (281; Fig 7H; ¶ [0132]) comprises aluminum ions (¶ [0048]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective date of the invention such that the semiconductor layer comprises silicon carbide and wherein the charge compensation region comprises hydrogen, aluminum or nitrogen dopant ions as taught by Schulze for in order to achieve an attractive super junction performance (¶ [0048]). Regarding claim 45, Fig 6h of Zhang discloses the charge compensation region (111/110a (left side); Fig 6h; ¶ [0050]) is spaced apart from the well region (112 (right side); Fig 6h; ¶ [0051]) in a vertical direction. Claim(s) 7-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20190140049; hereinafter Zhang) as applied to claim 1 and further in view of Wu et al (US 2021/0376075; hereinafter Wu) and Schulze et al (US 2020/0381253; hereinafter Schulze). Regarding claim 7, Zhang does not expressly disclose the semiconductor layer comprises silicon carbide and wherein the charge compensation region comprises inert ions. In the same field of endeavor, Fig 12 of Wu discloses a charge compensation/trapping layer (20; Fig 12; ¶ [0044]) can comprise non-electrical dopants such as argon (¶ [0044]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a charge compensation/trapping layer can comprise non-electrical dopants such as argon for the purpose of using non-electrical dopants in suppressing growth in the charge-trapping/compensation layer in subsequent high temperature processing steps (¶ [0044]). However Zhang in view of Wu does not expressly disclose the semiconductor layer comprises silicon carbide. In the same field of endeavor, Fig 7H of Schulze discloses a semiconductor layer (700; Fig 7H; ¶ [0125]) comprises silicon carbide (¶ [0125]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective date of the invention such that the semiconductor layer comprises silicon carbide and wherein the charge compensation region comprises hydrogen, aluminum or nitrogen dopant ions as taught by Schulze for in order to achieve an attractive super junction performance (¶ [0048]). Regarding claim 8, Zhang in view of Fig 12 of Wu (Wu in particular) discloses a charge compensation/trapping layer (20; Fig 12; ¶ [0044]) can comprise non-electrical dopants such as argon (¶ [0044]). Regarding claim 10, Zhang in view of Schulze does not expressly disclose the dopant ions comprise carbon and/or iron. In the same field of endeavor, Fig 12 of Wu discloses a charge compensation/trapping layer (20; Fig 12; ¶ [0044]) can comprise non-electrical dopants such as carbon (¶ [0044]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a charge compensation/trapping layer can comprise non-electrical dopants such as carbon for the purpose of using non-electrical dopants in suppressing growth in the charge-trapping/compensation layer in subsequent high temperature processing steps (¶ [0044]). Claim(s) 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20190140049; hereinafter Zhang) and in view of Schulze et al (US 2020/0381253; hereinafter Schulze) and further in view of Wu et al (US 2021/0376075; hereinafter Wu). Regarding claim 39, Zhang in view of Schulze does not expressly disclose the inert ions comprise He, Ne and/or Ar ions. In the same field of endeavor, Fig 12 of Wu discloses a charge compensation/trapping layer (20; Fig 12; ¶ [0044]) can comprise non-electrical dopants such as argon (¶ [0044]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a charge compensation/trapping layer can comprise non-electrical dopants such as argon for the purpose of using non-electrical dopants in suppressing growth in the charge-trapping/compensation layer in subsequent high temperature processing steps (¶ [0044]). Regarding claim 40, Zhang in view of Schulze does not expressly disclose the dopant ions that form deep level traps in the semiconductor layer comprise carbon and/or iron. In the same field of endeavor, Fig 12 of Wu discloses a charge compensation/trapping layer (20; Fig 12; ¶ [0044]) can comprise non-electrical dopants such as carbon (¶ [0044]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a charge compensation/trapping layer can comprise non-electrical dopants such as carbon for the purpose of using non-electrical dopants in suppressing growth in the charge-trapping/compensation layer in subsequent high temperature processing steps (¶ [0044]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Van Brunt et al (US 2022/0140132) Weyers et al (US 2022/0406928) Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RATISHA MEHTA/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Mar 07, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
95%
With Interview (+5.6%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 645 resolved cases by this examiner. Grant probability derived from career allowance rate.

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