Prosecution Insights
Last updated: August 17, 2026
Application No. 18/598,907

FERROELECTRIC 3D MEMORY BLOCK UNIT

Non-Final OA §102§103
Filed
Mar 07, 2024
Priority
Oct 20, 2023 — provisional 63/545,130
Examiner
MEHTA, RATISHA
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Electron Limited
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
571 granted / 638 resolved
+21.5% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 12m
Avg Prosecution
29 currently pending
Career history
661
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
47.7%
+7.7% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
12.8%
-27.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 638 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I in the reply filed on 4/28/2026 is acknowledged. Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/28/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 5, 7 and 10, 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae et al (US 2023/0068706; hereinafter Bae). Regarding claim 1, Fig 6 of Bae discloses a semiconductor device comprising: a first metal structure (130; Fig 6; ¶ [0064]) of a first gate electrode (130; Fig 6; ¶ [0064]); a gate dielectric structure (170; Fig 6; ¶ [0072]): extending (Fig 6) along a bottom surface of the first metal structure (130; Fig 6; ¶ [0064]); and surrounding a sidewall (Fig 6) of the first metal structure (130; Fig 6; ¶ [0064]); a semiconductor-behaving structure (220; Fig 6; ¶ [0092]): extending (Fig 6) along a bottom surface (Fig 6) of the gate dielectric structure (170; Fig 6; ¶ [0072]); and surrounding (Fig 6) a sidewall of the gate dielectric structure; a ferroelectric structure (160; Fig 6; ¶ [0065]) surrounding a sidewall of the semiconductor-behaving structure (220; Fig 6; ¶ [0092]); and a second gate electrode (110; Fig 6; ¶ [0059]) comprising a second metal structure (110; Fig 6; ¶ [0059]) in contact with the semiconductor-behaving structure (220; Fig 6; ¶ [0092]). Regarding claim 5, Figs 3 and 6 of Bae discloses a further dielectric structure (120; Figs 3 and 6) circumscribing the second metal structure (110; Fig 6; ¶ [0059]), wherein the ferroelectric structure is concentric to circumscribed by and in contact with the second metal structure (110; Fig 6; ¶ [0059]). Regarding claim 7, Fig 6 of Bae discloses the semiconductor-behaving structure (220; Fig 6; ¶ [0092]) comprises a conductive oxide (¶ [0092]). Regarding claim 10, Fig 6 of Bae discloses a semiconductor device comprising: a ferroelectric structure (160; Fig 6; ¶ [0065]) disposed around a second metal structure (110; Fig 6; ¶ [0059]); a semiconductor-behaving structure (220; Fig 6; ¶ [0092]) separated from a substrate, the semiconductor-behaving structure vertically extending along a sidewall of and laterally away from the ferroelectric structure; a gate dielectric structure (170; Fig 6; ¶ [0072]): extending (Fig 6) along an upper surface of the semiconductor behaving structure (220; Fig 6; ¶ [0092]); and surrounding (Fig 6) a sidewall of the semiconductor behaving structure; and a first metal structure (130; Fig 6; ¶ [0064]) surrounding a sidewall of the gate dielectric structure. Regarding claim 15, Fig 6 of Bae discloses the semiconductor-behaving structure (220; Fig 6; ¶ [0092]) comprises a conductive oxide (¶ [0092]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2, 9, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al (US 2023/0068706; hereinafter Bae) in view of Chang et al (US 2024/0276737; hereinafter Chang). Regarding claim 2, Bae does not expressly disclose a capacitor, the capacitor comprising a third metal structure separated from the metal structure by a capacitor dielectric structure. In the same field of endeavor, Fig 1 of Chang discloses a capacitor (200; Fig 1; ¶ [0017]) comprising a third metal structure (203; Fig 1; ¶ [0020]) separated from a metal structure (201 (portion of 201); Fig 1; ¶ [0020]) by a capacitor dielectric structure (202; Fig 1; ¶ [0020]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a capacitor is formed over the metal structure in order to form the ferroelectric random access memory which offers high density, low power consumption, high speed and low manufacturing cost. (¶ [0002]). Regarding claim 9, Bae in view of Chang as modified above in claim 2 discloses the capacitor dielectric structure (202; Fig 1; ¶ [0020] of Chang) and the gate dielectric structure (170; Fig 6; ¶ [0072]) comprise a same high-k dielectric material. Regarding claim 12, Bae does not expressly disclose a first dielectric structure interposed between a source/drain contact and the substrate. In the same field of endeavor, Fig 1 of Chang discloses a first dielectric structure (105; Fig 1; ¶ [0022]) interposed between a source/drain contact (105; Fig 1; ¶ [0022]) and the substrate (105; Fig 1; ¶ [0022]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a first dielectric structure interposed between a source/drain contact and the substrate in order to form the source/drain contacts plugs that are vertically extending (¶ [0022]). Claim(s) 3, 6, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al (US 2023/0068706; hereinafter Bae) in view of Chang et al (US 2024/0276737; hereinafter Chang) as applied to claim 2 and further in view of Lee et al (US 2024/0357832; hereinafter Lee) Regarding claim 3, Fig 6 of Bae discloses the first metal structure (130; Fig 6; ¶ [0064]) is connected to an electrical contact (131; Fig 6). However Bae does not expressly disclose an electrical contact electrically connected to the first metal structure vertically extending parallel to the capacitor dielectric structure, the electrical contact serving as a first terminal of the capacitor, wherein the third metal structure serves as a second terminal of the capacitor. In the same field of endeavor, Fig 1 of Chang discloses an electrical contact (201 (portion of 201); Fig 1; ¶ [0020]) serving as a first terminal (Fig 1; ¶ [0020]) of the capacitor (200; Fig 1; ¶ [0017]), wherein the third metal structure (203; Fig 1; ¶ [0020]) serves as a second terminal of the capacitor (Fig 1; ¶ [0020]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a capacitor is formed over the metal structure in order to form the ferroelectric random access memory which offers high density, low power consumption, high speed and low manufacturing cost. (¶ [0002]). However Bae in view of Chang does not expressly disclose electrical contact is vertically extending parallel to the capacitor dielectric structure. In the same field of endeavor, Fig 2 of Lee discloses a capacitor dielectric structure (400; Fig 2; ¶ [0039]) can extend vertically parallel to an electrical contact (390; Fig 2; ¶ [0039]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a capacitor dielectric structure is formed vertically in order to form the capacitor with the desired specifications and design (Fig 2). Regarding claim 6, Bae in view of Lee (Fig 2 in particular of Lee) discloses the third metal structure is connected to a plurality of further capacitor dielectric structures, the plurality of further capacitor dielectric structures configured to maintain a plurality of voltage levels. Regarding claim 11, Fig 6 of Bae discloses the first metal structure (130; Fig 6; ¶ [0064]) is connected to an electrical contact (131; Fig 6). However Bae does not expressly disclose a third metal structure separated from the first metal structure by a capacitor dielectric structure and an electrical contact electrically connected to the first metal structure vertically extending parallel to the capacitor dielectric structure, the electrical contact serving as a first terminal of the capacitor, wherein the third metal structure serves as a second terminal of the capacitor. In the same field of endeavor, Fig 1 of Chang discloses a capacitor (200; Fig 1; ¶ [0017]) comprising a third metal structure (203; Fig 1; ¶ [0020]) separated from a metal structure (201 (portion of 201); Fig 1; ¶ [0020]) by a capacitor dielectric structure (202; Fig 1; ¶ [0020]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a capacitor is formed over the metal structure in order to form the ferroelectric random access memory which offers high density, low power consumption, high speed and low manufacturing cost. (¶ [0002]). In the same field of endeavor, Fig 1 of Chang discloses an electrical contact (201 (portion of 201); Fig 1; ¶ [0020]) serving as a first terminal (Fig 1; ¶ [0020]) of the capacitor (200; Fig 1; ¶ [0017]), wherein the third metal structure (203; Fig 1; ¶ [0020]) serves as a second terminal of the capacitor (Fig 1; ¶ [0020]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a capacitor is formed over the metal structure in order to form the ferroelectric random access memory which offers high density, low power consumption, high speed and low manufacturing cost. (¶ [0002]). However Bae in view of Chang does not expressly disclose electrical contact is vertically extending parallel to the capacitor dielectric structure. In the same field of endeavor, Fig 2 of Lee discloses a capacitor dielectric structure (400; Fig 2; ¶ [0039]) can extend vertically parallel to an electrical contact (390; Fig 2; ¶ [0039]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a capacitor dielectric structure is formed vertically in order to form the capacitor with the desired specifications and design (Fig 2). Regarding claim 13, Bae in view of Chang and Lee as modified above in claim 11 discloses the capacitor dielectric structure (202; Fig 1; ¶ [0020] of Chang) and the gate dielectric structure (170; Fig 6; ¶ [0072]) comprise a same high-k dielectric material. Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bae et al (US 2023/0068706; hereinafter Bae) in view of Lee et al (US 2024/0357832; hereinafter Lee). Regarding claim 4, Fig 3 of Bae discloses the first metal structure (130; Fig 6; ¶ [0064]) is concentric to the sidewall of the gate dielectric structure (170; Fig 6; ¶ [0072]); the gate dielectric structure (170; Fig 6; ¶ [0072]) is concentric to the sidewall of the semiconductor-behaving structure (220; Fig 6; ¶ [0092]); the semiconductor-behaving structure (220; Fig 6; ¶ [0092]) is concentric to the ferroelectric structure (160; Fig 6; ¶ [0065]). However Bae does not expressly disclose a capacitor dielectric structure is vertically spaced from the gate dielectric structure, the semiconductor-behaving structure and the ferroelectric structure. In the same field of endeavor, Fig 2 of Lee discloses forming a capacitor dielectric structure (400; Fig 2; ¶ [0039]) vertically spaced from rest of the structure (Fig 2). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a capacitor dielectric structure is formed vertically in order to form the capacitor with the desired specifications and design (Fig 2). Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 8, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a first source/drain contact extends beyond a lateral extreme of the semiconductor-behaving structure; and the semiconductor-behaving structure extends beyond the first source/drain contact opposite of the lateral extreme”. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Chen et al (US 2024/0040799) Lin et al (US 2023/0207695) Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RATISHA MEHTA/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Mar 07, 2024
Application Filed
Jul 13, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
95%
With Interview (+5.7%)
1y 12m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 638 resolved cases by this examiner. Grant probability derived from career allowance rate.

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