DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 objected to because of the following informalities. Claim 10 contains the phrase, “the second plurality of thermal vias of the second die is disposed as the second pitch,” in lines 1-2 of the claim. For the purpose of this office action, the phrase is interpreted to have the following meaning: the second plurality of thermal vias of the second die is disposed at the second pitch. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 recites the limitation "the total number of thermal vias of the second die " in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7-10, and 21-24 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elliott et al. (US 7875952 B1; hereinafter referred to as "Elliott”).
Re claim 1: Elliott teaches an integrated circuit (IC) structure (FIG. 4; col. 4: lines 48-49), comprising: a first die (annotated FIG. 4: el. 1st die | annotated FIG. 4 provided below), the first die comprising: a first transistor device (FIG. 4: el. 301) formed on a substrate (FIG. 4: el. 108| substrate of first die formed of lower active layer 108 as labelled in FIG. 1); a first multi-layer interconnect (MLI) over the substrate (annotated FIG. 4: el. 1st MLI | annotated FIG. 4 provided below), wherein the first MLI includes a plurality of metal lines and interposing metal vias (FIG. 4), wherein the first MLI is electrically coupled to the first transistor device (annotated FIG. 4: el. 1st MLI, 301 | annotated FIG. 4 provided below); and a first plurality of thermal vias laterally adjacent the first MLI (annotated FIG. 4: el. 1st thermal vias | annotated FIG. 4 provided below); a thermal bonding layer over the first die (FIG. 1-4: el. 110| bonding layer 110 on the first die is a thermal heat spreading layer); and a second die over the thermal bonding layer (annotated FIG. 4: el. 2nd die| annotated FIG. 4 provided below), the second die comprising: a second transistor device (FIG. 4: el. 102) formed on another substrate (FIG. 4: el. 103; col. 6: lines 22-24| another substrate formed of silicon base wafer); a second MLI over the another substrate (annotated FIG. 4: el. 2nd MLI| annotated FIG. 4 provided below), wherein the second MLI includes a plurality of metal lines and interposing metal vias (FIG. 4), wherein the second MLI is electrically coupled to the second transistor device (annotated FIG. 4: el. 102, 2nd MLI| annotated FIG. 4 provided below); and a second plurality of thermal vias laterally adjacent the second MLI (annotated FIG. 4: el. 2nd thermal vias, 2nd MLI| annotated FIG. 4 provided below), wherein the second plurality of thermal vias is less than the first plurality of thermal vias (annotated FIG. 4: el. 1st thermal vias, 2nd thermal vias| top-down cross-sectional area of plurality of 2nd thermal vias is less than cross-sectional area of plurality of 1st thermal vias; this interpretation of a plurality of vias being “less” than another plurality of vias by being “less” than in cross-sectional area from a top-down view is consistent with an interpretation provided by the specification of the instant application (para. 51: sentence 13 of instant application).
PNG
media_image1.png
696
856
media_image1.png
Greyscale
Re claim 1 (second mapping): Elliott teaches an integrated circuit (IC) structure (FIG. 4; col. 4: lines 48-49), comprising: a first die (annotated FIG. 4: el. 1st die | annotated FIG. 4 provided below), the first die comprising: a first transistor device (FIG. 4: el. 301) formed on a substrate (FIG. 4: el. 108| substrate of first die formed of lower active layer 108 as labelled in FIG. 1); a first multi-layer interconnect (MLI) over the substrate (annotated FIG. 4: el. 1st MLI | annotated FIG. 4 provided below), wherein the first MLI includes a plurality of metal lines and interposing metal vias (FIG. 4), wherein the first MLI is electrically coupled to the first transistor device (annotated FIG. 4: el. 1st MLI, 301 | annotated FIG. 4 provided below); and a first plurality of thermal vias laterally adjacent the first MLI (annotated FIG. 4: el. 1st thermal vias | annotated FIG. 4 provided below); a thermal bonding layer over the first die (FIG. 1-4: el. 110| bonding layer 110 on the first die is a thermal heat spreading layer); and a second die over the thermal bonding layer (annotated FIG. 4: el. 2nd die| annotated FIG. 4 provided below), the second die comprising: a second transistor device (FIG. 4: el. 102) formed on another substrate (FIG. 4: el. 103; col. 6: lines 22-24| another substrate formed of silicon base wafer); a second MLI over the another substrate (annotated FIG. 4: el. 2nd MLI| annotated FIG. 4 provided below), wherein the second MLI includes a plurality of metal lines and interposing metal vias (FIG. 4), wherein the second MLI is electrically coupled to the second transistor device (annotated FIG. 4: el. 102, 2nd MLI| annotated FIG. 4 provided below); and a second plurality of thermal vias laterally adjacent the second MLI (annotated FIG. 4: el. 2nd thermal vias, 2nd MLI| annotated FIG. 4 provided below; a plurality of 2nd thermal vias formed of a plurality of vias which are electrically connected to transistors 102 and are also thermally connected to the thermal bonding layer 110), wherein the second plurality of thermal vias is less than the first plurality of thermal vias (annotated FIG. 4: el. 1st thermal vias, 2nd thermal vias| top-down cross-sectional area plurality of 2nd thermal vias is less than cross-sectional area of plurality of 1st thermal vias; this interpretation of a plurality of vias being “less” than another plurality of vias by being “less” than in cross-sectional area from a top-down view is consistent with an interpretation provided by the specification of the instant application (para. 51: sentence 13 of instant application).
PNG
media_image2.png
683
1066
media_image2.png
Greyscale
Re claim 7: Elliott teaches the IC structure of claim 1, wherein the first plurality of thermal vias laterally adjacent the first MLI is disposed in a first region of the first die (annotated FIG. 4: el. 1st thermal vias| annotated FIG. 4 provided in Re claim 1 (second mapping) section) and a third plurality of thermal vias is disposed in a second region of the first die (annotated FIG. 4: el. 3rd thermal vias| a plurality of 3rd thermal vias formed of a plurality of vias which are electrically connected to transistors 103 and are also thermally connected to the thermal bonding layer 110; annotated FIG. 4 provided in Re claim 1 (second mapping) section).
Re claim 8: Elliott teaches the IC structure of claim 7, wherein the first plurality of thermal vias has a greater area than the third plurality of thermal vias (annotated FIG. 4: el. 1st thermal vias, 3rd thermal vias| top-down cross-sectional area of plurality of 3rd thermal vias is less than cross-sectional area of 1st thermal vias; this interpretation of a plurality of vias being “less” than another plurality of vias by being “less” than in cross-sectional area from a top-down view is consistent with an interpretation provided by the specification of the instant application (para. 51: sentence 12 of instant application).
Re claim 9: Elliott teaches the IC structure of claim 7, wherein the first plurality of thermal vias is disposed at a first pitch and the third plurality of thermal vias is disposed at a second pitch, the second pitch greater than the first pitch (annotated FIG. 4: el. 1st thermal vias, 3rd thermal vias| the 1st thermal vias are vertically separated by a horizontal metal layer and the separation pitch is small, while the 3rd thermal vias have a horizontal separation which a large separation pitch; annotated FIG. 4 provided in Re claim 1 (second mapping) section).
Re claim 10: Elliott teaches the IC structure of claim 9, wherein the second plurality of thermal vias of the second die is disposed at the second pitch (annotated FIG. 4: el. 2nd thermal vias| the 2nd thermal vias have a horizontal separation which is the same separation pitch possessed by the 3rd thermal vias; annotated FIG. 4 provided in Re claim 1 (second mapping) section).
Re claim 1 (third mapping): Elliott teaches an integrated circuit (IC) structure (FIG. 4; col. 4: lines 48-49), comprising: a first die (annotated FIG. 4: el. 1st die | annotated FIG. 4 provided below), the first die comprising: a first transistor device (FIG. 4: el. 102) formed on a substrate (FIG. 4: el. 103; col. 6: lines 22-24| another substrate formed of silicon base wafer); a first multi-layer interconnect (MLI) over the substrate (annotated FIG. 4: el. 1st MLI | annotated FIG. 4 provided below), wherein the first MLI includes a plurality of metal lines and interposing metal vias (FIG. 4), wherein the first MLI is electrically coupled to the first transistor device (annotated FIG. 4: el. 102, 1st MLI| annotated FIG. 4 provided below); and a first plurality of thermal vias laterally adjacent the first MLI (annotated FIG. 4: el. 1st thermal vias | annotated FIG. 4 provided below); a thermal bonding layer over the first die (FIG. 1-4: el. 110| bonding layer 110 is a thermal heat spreading layer which is bonded to the first die); and a second die over the thermal bonding layer (annotated FIG. 4: el. 2nd die| annotated FIG. 4 provided below), the second die comprising: a second transistor device (FIG. 4: el. 301) formed on another substrate (FIG. 4: el. 108| substrate of first die formed of lower active layer 108 as labelled in FIG. 1); a second MLI over the another substrate (annotated FIG. 4: el. 2nd MLI| annotated FIG. 4 provided below), wherein the second MLI includes a plurality of metal lines and interposing metal vias (FIG. 4), wherein the second MLI is electrically coupled to the second transistor device (annotated FIG. 4: el. 2nd MLI, 301 | annotated FIG. 4 provided below); and a second plurality of thermal vias laterally adjacent the second MLI (annotated FIG. 4: el. 2nd thermal vias, 2nd MLI| annotated FIG. 4 provided below), wherein the second plurality of thermal vias is less than the first plurality of thermal vias (annotated FIG. 4: el. 1st thermal vias, 2nd thermal vias| quantity of plurality of 2nd thermal vias is less than quantity of plurality of 1st thermal vias; this interpretation of a plurality of vias being “less” than another plurality of vias by being “less” than in quantity is consistent with an interpretation provided by the specification of the instant application (para. 51: sentence 12 of instant application).
PNG
media_image3.png
691
856
media_image3.png
Greyscale
Re claim 21: Elliott teaches an integrated circuit (IC) structure (FIG. 4; col. 4: lines 48-49), comprising: a first transistor device (FIG. 4: el. 301) on a first die (annotated FIG. 4: el. 1st die |annotated FIG. 4 provided below) and a second transistor device (FIG. 4: el. 102) on a second die (annotated FIG. 4: el. 2nd die |annotated FIG. 4 provided below); a first plurality of thermal vias (annotated FIG. 4: el. 1st thermal vias |annotated FIG. 4 provided below) on the first die adjacent the first transistor device and a second plurality of thermal vias (annotated FIG. 4: el. 2nd thermal vias |annotated FIG. 4 provided below) on the second die adjacent the second transistor device, wherein the first plurality of thermal vias has a greater area than the second plurality of thermal vias (annotated FIG. 4: el. 1st thermal vias, 2nd thermal vias| top-down cross-sectional area of plurality of 2nd thermal vias is less than top-down cross-sectional area of plurality of 1st thermal vias); a thermal bonding layer on a surface of the first die (FIG. 1-4: el. 110| bonding layer 110 on the first die is a thermal heat spreading layer); and the second die attached to the thermal bonding layer (FIG. 1, annotated FIG. 4: el. 2nd die| 2nd die bonded to thermal bonding layer 110).
PNG
media_image4.png
584
1020
media_image4.png
Greyscale
Re claim 22: Elliott teaches the IC structure of claim 21, further comprising: a multi-layer interconnect (MLI) on the first die (annotated FIG. 4: el. 1st MLI| annotated FIG. 4 provided in Re claim 21 section).
Re claim 23: Elliott teaches the IC structure of claim 21, wherein the thermal bonding layer interfaces an upper most surface of the first plurality of thermal vias (annotated FIG. 4: el. ‘an uppermost surface of the plurality of 1st plurality of thermal vias’| annotated FIG. 4 provided in Re claim 21 section; an uppermost surface of the 1st plurality of thermal vias interfaces the thermal bonding layer 110 (thermal bonding layer 110 as labelled in FIG. 1)).
Re claim 24: Elliott teaches the IC structure of claim 23, wherein a lower surface of the first plurality of thermal vias interfaces an interlayer dielectric (annotated FIG. 4: el. ‘a lower surface of the 1st plurality of thermal vias’| annotated FIG. 4 provided in Re claim 21 section; a lower surface of the 1st plurality of thermal vias interfaces the intermetal dielectric contained between the metal lines and vias of the 1st die).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Elliott as applied to claim 1 above (Re claim 1 section), and further in view of Dutta et al. (US PGPub 20210151428 A1; hereinafter referred to as "Dutta”).
Re claim 2: Elliott teaches the IC structure of claim 1, wherein the first transistor device is a high- power transistor (col. 5: lines 43-57| transistor 301 is a III-V transistor and Elliott teaches the III-V transistor as a high frequency InP HBT; the interpretation of a high-speed transistor as being a high-power transistor is consistent with an interpretation of the instant application (para. 27: second to last sentence)). Elliott teaches connecting a first III-V transistor die with a second CMOS transistor die, but fails to teach and wherein the second transistor device is a logic transistor.
In a similar field of endeavor, Dutta teaches integrating a first III-V transistor die with a second CMOS transistor die (para. abstract, 23, 26-27). Dutta further teaches the integration of CMOS logic transistors and the III-V high voltage transistors (para. 23) and teaches a benefit of integrating heterogeneous transistors such as CMOS logic transistors and III-V high voltage transistors is a fabrication cost benefit due to the fabrication of the heterogeneous transistors in the same facility (para. 23, 26-27).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Elliott with the teachings of Dutta, to enable using the CMOS logic transistor of Dutta in the IC structure of Elliott, for the benefit of reduced production costs in integrating power devices with the control logic of the devices.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Elliott as applied to claim 1 above (Re claim 1 (third mapping) section), and further in view of Huang et al. (US PGPub 20230066284 A1; hereinafter referred to as "Huang”).
Re claim 3: Elliott teaches the IC structure of claim 1, wherein the thermal bonding layer is integrated on a III-V substrate and spreads and diffuses heat from the IC (col. 5: lines 21-24; col. 6: lines 22-29). Elliott is silent to the specific material of the thermal bonding layer.
In a similar field of endeavor, Huang teaches a thermal bonding layer for diffusing heat in a semiconductor structure (para. 44). Huang teaches a thermal bonding layer for diffusing heat with a thermal conductivity of 5-500 W/m-K formed of aluminum nitride or one of seven other high thermal conductivity dielectric materials (para. 20). One of ordinary skill in the art would have recognized the finite number of predictable solutions for forming a dielectric thermal bonding layer for diffusing heat as taught by Huang. Absent unexpected results, it would have been obvious to try each of the eight dielectric thermal bonding materials to yield an AlN thermal bonding layer with improved bonding and heat diffusion. Huang further teaches a benefit of a thermal bonding layer with a material such as aluminum nitride having a thermal conductivity of 5-500 W/m-K is improved heat diffusion and the ability to diffuse heat away from layers with a lower thermal conductivity such as interconnect layers (para. 20, 40).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Elliott with the teachings of Huang, to enable using AlN, as taught by Huang, in the thermal bonding layer of the IC structure of Elliott, for the benefit of improved diffusion of heat from interconnect materials.
Re claim 4: The combination of Huang and Elliott teaches the IC structure of claim 3, wherein the AlN extends from a dielectric layer of the first MLI of the first die to the another substrate of the second die (Elliott – FIG. 1, annotated FIG. 4: el. 110, 108, 1st MLI| annotated FIG. 4 provided in Re claim 1 (third mapping) section; as labelled in FIG. 1 and structurally shown in annotated FIG. 4, the thermal bonding layer 110 extends substantially from the upper surface of the upper dielectric of the 1st MLI of the first die to the another substrate 108 of the second die).
Claims 11-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Elliott in view of Huang.
Re claim 11: Elliott teaches an integrated circuit (IC) structure (FIG. 4; col. 4: lines 48-49), comprising: a plurality of vertically stacked dies (annotated FIG. 4: el. 1st die, 2nd die); a thermal bonding layer extending between a first die and a second die of the plurality of vertically stacked dies (FIG. 1, annotated FIG. 4: el. 110 | bonding layer of the first die 110 is a thermal heat spreading layer); and a plurality of thermal vias on at least one of the first die (annotated FIG. 4: el. 1st thermal vias| annotated FIG. 4 provided below) or the second die, wherein the plurality of thermal vias are disposed adjacent a high-power transistor device (FIG. 4: el. 301; col. 5: lines 43-57| transistor 301 is a III-V transistor and Elliott teaches the III-V transistor as a high frequency InP HBT; the interpretation of a high-speed transistor as being a high-power transistor is consistent with an interpretation of the instant application (para. 27: second to last sentence)). Elliott fails to teach wherein the thermal bonding layer comprises a material having a thermal conductivity between approximately 10 and 500 W/m/K.
In a similar field of endeavor, Huang teaches a thermal bonding layer for diffusing heat in a semiconductor structure (para. 44). Huang teaches a thermal bonding layer for diffusing heat comprising a material having a thermal conductivity between approximately 10 and 500 W/m/K (para. 20| Huang specifically discloses a thermal bonding layer comprising a material having a thermal conductivity of 5-500 W/m-K and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Huang further teaches a benefit of a thermal bonding layer with a material such as aluminum nitride having a thermal conductivity of 5-500 W/m-K is improved heat diffusion and the ability to diffuse heat away from layers with a lower thermal conductivity such as interconnect layers (para. 20, 40).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Elliott with the teachings of Huang, to enable using a material having a thermal conductivity between approximately 10 and 500 W/m/K, as taught by Huang, in the thermal bonding layer of the IC structure of Elliott, for the benefit of improved diffusion of heat from interconnect materials.
PNG
media_image5.png
698
1112
media_image5.png
Greyscale
Re claim 12: The combination of Elliott and Huang teaches the IC structure of claim 11, wherein the material is AlN, diamond, boron nitride, Al2O3, BeO, or combinations thereof (Huang - para. 20| Huang teaches a thermal bonding layer for diffusing heat with a thermal conductivity of 5-500 W/m-K formed of aluminum nitride, carbon, boron nitride, Al2O3, BeO, or one of 3 other high thermal conductivity dielectric materials. One of ordinary skill in the art would have recognized the finite number of predictable solutions for forming a dielectric thermal bonding layer for diffusing heat as taught by Huang. Absent unexpected results, it would have been obvious to try each of the eight dielectric thermal bonding materials to yield a thermal bonding layer with improved bonding and heat diffusion).
Re claim 14: The combination of Elliott and Huang teaches the IC structure of claim 11, wherein an end of each of the plurality of thermal vias interfaces the thermal bonding layer (Elliott - annotated FIG. 4: el. 1st thermal vias| annotated FIG. 4 provided in Re claim 11 section; an end of each of the thermal vias interfaces the thermal bonding layer either directly or through contact with a vertically adjacent thermal via).
Re claim 15: The combination of Elliott and Huang teaches the IC structure of claim 11, wherein a total number of thermal vias of the first die is different than the total number of thermal vias of the second die (Elliott – annotated FIG. 4, provided in Re claim 11 section| total number of thermal vias which are vias having a thermal connection to the thermal bonding layer 110 is smaller in the first die than in the second die).
Re claim 16: The combination of Elliott and Huang teaches the IC structure of claim 11, wherein the plurality of thermal vias is on a first region of the first die (Elliott – annotated FIG. 4: el. 1st thermal vias, 1st region| annotated FIG. 4 provided in Re claim 11 section) and a second plurality of thermal vias is on a second region of the first die (Elliott – annotated FIG. 4: el. 2nd thermal vias, 2nd region| annotated FIG. 4 provided in Re claim 11 section), the first region having a greater density of thermal vias than the second region (lateral density of thermal vias is greater in the first region than the second region).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights