DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, claims 1-5 and 17-20 in the reply filed on 07/12/26 is acknowledged.
Newly submitted claims 21-31 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: The new claims have features not described in the elected Invention which are "the first source/drain feature and the second source/drain feature are formed in lower parts of the first source/drain trench and the second source/drain trench, respectively."
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21 - 31 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/08/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 17-20 are rejected under 35 U.S.C. 102 as being anticipated by Xie et al. ( US 2025/0285964 A1; hereinafter Xie )
Regarding claim 1, Xie teaches a semiconductor structure ( Fig. 1A cross-sectional view of a semiconductor structure ), comprising: a first transistor ( [0040] FIGS. 1A and 1B, a semiconductor structure 100 includes a stacked structure of a plurality of upper transistors (also referred to herein as “second transistors”) stacked on a plurality of lower transistors (also referred to herein as “first transistors”)), comprising: first nanostructures ( [0046] As used herein, “frontside or “first side” refers to a side on top of the second semiconductor substrate 103 and/or in front of, on top of or in an upward direction from the stacked structure of the upper nanosheet transistors stacked on the lower nanosheet transistors in the orientation shown in the cross-sectional figures ), wherein the first nanostructures are spaced apart from each other in a Z-direction ( [0049] First n-type source/drain regions 105 and first p-type source/drain regions 106 are epitaxially grown between the nanosheet stacks corresponding to the lower transistors and second n-type source/drain regions 115 and second p-type source/drain regions 116 are epitaxially grown between the nanosheet stacks corresponding to the lower transistors ); and a first source/drain feature ( Fig. 1A #105 ) and a second source/drain feature ( Fig. 1A #106 ), attached to opposite sides of the first nanostructures in an X-direction ( as shown in Fig. 1A ); a second transistor ( as discussed above ) vertically overlapping the first transistor ( as discussed above ), wherein the second transistor comprises: second nanostructures vertically overlapping the first nanostructures ( as shown in Fig. 1A – 1B ), wherein the second nanostructures are spaced apart from each other in the Z-direction ( as discussed above ); and a third source/drain feature and a fourth source/drain feature ( [0041] the upper transistors further include second n-type source/drain regions 115 and second p-type source/drain regions 116 stacked over the first n-type source/drain regions 105 and first p-type source/drain regions 106 ), attached to opposite sides of the second nanostructures in the X-direction ( as shown in Fig. 1A ) and vertically overlapping the first source/drain feature and the second source/drain feature ( as shown in Fig. 1A ), respectively; a gate structure ( Fig. 1A gate structures 140 and 141 ) wrapped around the first nanostructures ( [0041] the lower transistors include a plurality of first channel layers 107 alternately stacked with and surrounded by first gate structures 140 ) and the second nanostructures ( [0041] The upper transistors include a plurality of second channel layers 117 alternately stacked with and surrounded by second gate structures 141 ); a first source/drain contact ( Fig. 2A frontside source/drain contacts 155 ), extending through the third source/drain feature ( Fig. 2A #115 ) and partially extending into the first source/drain feature ( Fig. 2A #105 ) ; and a second source/drain contact ( Fig. 2A #120 ) extending into the first source/drain feature ( Fig. 2A #105 ).
Regarding claim 2, Xie teaches the semiconductor structure of claim 1 ( as discussed above ), further comprising: a first interlayer dielectric (ILD) layer ( Fig. 1A ILD layer 130 ), surrounding the first source/drain feature ( Fig. 1A #105 ) and the second source/drain feature ( Fig. 1A #106 ), and separating the first source/drain feature ( Fig. 1A #105 ) and the second source/drain feature ( Fig. 1A #106 ) from the third source/drain feature ( Fig. 1A #115 ) and the fourth source/drain feature ( Fig. 1A #116 ) , wherein the first source/drain contact further extends through the first ILD layer ( as shown in Fig. 1A ).
Regarding claim 3, Xie teaches the semiconductor structure of claim 1, further comprising: a first silicide layer ( [0067] Conductive material of the wires 150, deep contacts 151, frontside deep gate contacts 152, frontside shallow gate contacts 153, frontside source/drain vias 154 and frontside source/drain contacts 155 includes, for example, a silicide layer, such as Ni, Ti, NiPt, etc., a metal adhesion layer, such as TiN, and a conductive metal fill layer, such as W, Al, Co, Ru, Cu, etc., and can be deposited using, for example, a deposition technique such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering and/or plating, followed by a planarization process such as, CMP to remove excess portions of the metal layers from on top of the ILD layer 130 ), formed on an interface between the first source/drain contact and the third source/drain feature ( as shown in Figs. 2A and 2B ); and a second silicide layer ( [0073] The metal layers include, for example, a silicide layer, such as Ni, Ti, NiPt, etc., a metal adhesion layer, such as TiN, and a conductive metal fill layer, such as W, Al, Co, Ru, Cu, etc., and can be deposited using, for example, a deposition technique such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering and/or plating, followed by a planarization process such as, CMP to remove excess portions of the metal layers from on top of the backside ILD layer 170 ), formed on an interface between the first source/drain contact and the first source/drain feature( as shown in Figs. 6A and 6B )
Regarding claim 4, Xie teaches the semiconductor structure of claim 3 ( as discussed above ), further comprising: a third silicide layer ( [0080] Conductive material of the wires 180, backside source/drain contacts 175, first backside vias 176, second backside vias 178, third backside vias 179 and the intermediate backside contacts 177 includes, for example, a silicide layer, such as Ni, Ti, NiPt, etc., a metal adhesion layer, such as TiN, and a conductive metal fill layer, such as W, Al, Co, Ru, Cu, etc., and can be deposited using, for example, a deposition technique such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering and/or plating, followed by a planarization process such as, CMP to remove excess portions of the metal layers from on top of the backside ILD layer 170 or additional backside ILD layer 170′ ), formed on an interface between the second source/drain contact and the first source/drain feature ( as shown in Figs. 7A and 7B )
Regarding claim 5, Xie teaches the semiconductor structure of claim 4, wherein a horizontal portion of the second silicide layer ( Fig. 7A #175 ) formed on a bottom surface of the first source/drain contact ( as shown in Fig 7A ) is separated from a horizontal portion of the third silicide layer ( Fig. 7A #177 ) formed on a top surface of the second source/drain contact by a portion of the first source/drain feature ( as shown in Fig. 7A )
Regarding claim 17, Xie teaches a method of forming semiconductor structure, comprising: forming a fin structure extending in an X-direction over a substrate ( Fig. 1B first gate isolation region 143 ), wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked in a Z-direction ( [0093] In another embodiment, a semiconductor device includes a first device layer, a second device layer stacked on the first device layer, and a plurality of gate isolation regions disposed through respective gate structures of the second device layer ); forming a dummy gate structure over the fin structure and extending in a Y-direction ( [0094] The plurality of gate isolation regions may respectively include at least one dielectric layer disposed between a gate contact of the plurality of gate contacts and a gate structure of the second device layer. A plurality of additional gate isolation regions may be disposed through respective gate structures of the first device layer, wherein the plurality of additional gate isolation regions are offset from the plurality of gate isolation regions ); forming a first source/drain feature ( Fig. 2A #105 ) and a second source/drain feature ( Fig. 2A #106 ) on opposite sides of the dummy gate structure in the X-direction ( Fig. 2B #140), wherein the first source/drain feature ( Fig. 2A #105 ) and the second source/drain feature ( Fig. 2A #106 ) are attached to a first group of the second semiconductor layers ( as shown in Fig. 2A ); forming a third source/drain feature ( Fig. 2A #115 ) and a fourth source/drain feature ( Fig. 2A #116 ) over the first source/drain feature ( Fig. 2A #105 ) and the second source/drain feature ( Fig. 2A #106 ), respectively, wherein the third source/drain feature ( Fig. 2A #115 ) and the fourth source/drain feature ( Fig. 2A #116 ) are attached to a second group of the second semiconductor layers ( as shown in Fig. 2A ); forming a first trench ( Fig. 2A isolation regions 104 ) extending through the third source/drain feature ( Fig. 2A #115 ) and partially extending into the first source/drain feature ( Fig. 2A #105 ); filling the first trench with a first conductive material to form a first source/drain contact ( Fig. 2A #120 ); forming a second trench extending through the substrate ( as shown in Fig. 2A 150 ) and partially extending into the first source/drain feature ( Fig. 2A #105 ); and filling the second trench ( Fig. 2A #150 ) with a second conductive material to form a second source/drain contact ( Fig. 2A 155).
Regarding claim 18, Xie teaches the method of claim 17 ( as discussed above ), further comprising: before filling the first trench ( Fig. 2A #104 ) with the first conductive material ( Fig. 2A #120 ), forming a first silicide layer ( [0067] Conductive material of the wires 150, deep contacts 151, frontside deep gate contacts 152, frontside shallow gate contacts 153, frontside source/drain vias 154 and frontside source/drain contacts 155 includes, for example, a silicide layer, such as Ni, Ti, NiPt, etc., a metal adhesion layer, such as TiN, and a conductive metal fill layer, such as W, Al, Co, Ru, Cu, etc., and can be deposited using, for example, a deposition technique such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering and/or plating, followed by a planarization process such as, CMP to remove excess portions of the metal layers from on top of the ILD layer 130 ) on a surface of the first source/drain feature ( Fig. 2A #105 ) exposed by the first trench ( Fig. 2A #104 ); and before filling the second trench ( Fig. 2A #150 ) with the second conductive material ( Fig. 2A #155), forming a second silicide layer ( [0073] The metal layers include, for example, a silicide layer, such as Ni, Ti, NiPt, etc., a metal adhesion layer, such as TiN, and a conductive metal fill layer, such as W, Al, Co, Ru, Cu, etc., and can be deposited using, for example, a deposition technique such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering and/or plating, followed by a planarization process such as, CMP to remove excess portions of the metal layers from on top of the backside ILD layer 170 ) on a surface of the third source/drain feature ( Fig. 2A #115 ) exposed by the first trench (Fig. 2A #104 ).
Regarding claim 19, Xie teaches the method of claim 18 ( as discussed above ), wherein the forming the second trench ( Fig 2A #150 ) comprises: etching through the substrate ( Fig. 2A #101 ) and partially etching the first source/drain feature ( Fig. 2A #105 ) to form the second trench ( Fig. 2A #150 ), wherein after forming the second trench ( Fig. 2A #150 ), a remaining portion of the first source/drain feature ( Fig. 2A #105 ) remains and separates a top surface of the second trench ( Fig. 2A #150 ) from a horizontal portion of the first silicide layer ( as discussed in [0067] ) formed on a bottom surface of the first source/drain contact ( Fig. 2A #120 ).
Regarding claims 20, Xie teaches the method of claim 19 ( as discussed above ), further comprising: before filling the second trench ( Fig. 2A #150 ) with the second conductive material ( Fig. 2A #155 ) , forming a third silicide layer ( as discussed in [0080] ) on a surface of the first source/drain feature ( Fig. 2A #105 ) exposed by the second trench ( Fig. 2A #150 ) - wherein the forming the third silicide layer ( as discussed above ) converts the remaining portion of the first source/drain feature ( Fig. 2A #105 ) into a horizontal portion of the third silicide layer ( as discussed above ) formed on the top surface of the second trench ( Fig. 2A #150 ), such that the horizontal portion of the third silicide layer ( as discussed above ) formed on the top surface of the second trench ( Fig. 2A #150 ) is in direct contact with the horizontal portion of the first silicide layer ( as described in [0067] ) formed on the bottom surface of the first source/drain contact ( Fig. 2A #120 ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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