Prosecution Insights
Last updated: August 16, 2026
Application No. 18/600,172

INTEGRATED CIRCUIT PACKAGES WITH THERMAL RESERVOIR DIES AND METHODS OF FORMING THE SAME

Non-Final OA §102§103
Filed
Mar 08, 2024
Priority
Dec 26, 2023 — provisional 63/614,700
Examiner
HARBOTTLE, CHARLOTTE ELIZABETH
Art Unit
4100
Tech Center
4100
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
13 currently pending
Career history
5
Total Applications
across all art units

Statute-Specific Performance

§103
78.6%
+38.6% vs TC avg
§102
14.3%
-25.7% vs TC avg
§112
7.1%
-32.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group II, claims 16-20 in the reply filed on July 14th 2026 is acknowledged. Therefore claims 1-15 are hereby withdrawn. Applicant’s amendment to add new claims 21-35 is also acknowledged and they correspond to elected Group II. Therefore 16-35 are examined below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 16-18, & 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (US 20230378152 A1). Regarding Claim 16, Hsu et al. teaches a method comprising: Encapsulating an interconnection die (See the die, 130, in Fig. 18. The die, 130, serves as an interconnection die since it connects to the other dies) and a thermal reservoir die (The dummy dies, 330, in Fig. 18. Paragraph 0040 describes that the dummy dies, 330, serve as heat dissipating elements for the for the package) with an encapsulant (Fig 18 shows the encapsulant, 140’, encapsulating both the interconnection die, 130, and the thermal reservoir die, 330), a front-side surface of the encapsulant being substantially coplanar with a front-side surface of the thermal reservoir die (Figure 18 shows the encapsulant, 140’, being coplanar with the thermal reservoir die, 330); Forming a front-side redistribution structure on the front-side surface of the encapsulant and the front-side surface of the thermal reservoir die (Paragraph 0049 describes the formation of the front-side redistribution structure, 118. Fig. 18 shows the redistribution structure, 118, formed on the front side surface of the thermal reservoir die, 330, and the encapsulant, 140’), the front-side redistribution structure comprising first-redistribution lines that are connected to the interconnection die (Figure 18 shows the redistribution lines, 118b, attached to the interconnection die, 130); and PNG media_image1.png 451 750 media_image1.png Greyscale Attaching a logic device and a memory device to the front-side redistribution structure, the memory device overlapping the thermal reservoir die in a plan view (The annotated Fig 18 below shows the regions that serve as the memory device and the logic device. These lines are used as reference for the plan view of the device, showing that they would overlap the thermal die in plan view, paragraph 0068). Regarding Claim 17, Hsu et al. teaches that the thermal reservoir die is confined within edges of the memory device in the plan view (The annotated Fig 18 at the bottom of the rejection for claim 1 shows that the thermal device is confined within the edges of the memory device in plan view). Regarding Claim 18, Hsu et al. teaches that the logic device and the memory device each overlap the interconnection die in the plan view (The annotated Fig 18 at the bottom of the rejection for claim 1 shows that the memory and logic device both overlap the interconnection die in plan view). Regarding Claim 21, Hsu et al. teaches that the thermal reservoir die is electrically nonfunctional (Paragraph 0027 describes the thermal reservoir die, 330, as a dummy die. It is known in the art that dummy dies are dies that do not contain active circuits such as transistors or diodes). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 19-20, 23-31, & 33-35 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20230378152 A1) in view of Tsou et al. (US 20210375768 A1) Regarding Claim 19, Hsu et al. teaches forming a back-side redistribution structure on a back-side surface of the encapsulant and a back-side surface of the thermal reservoir die (Fig 18 shows a redistribution structure, 150, on the back side surface of the encapsulant, 140’, and the thermal reservoir die, 330); Hsu et al. does not teach attaching a package substrate to the back-side redistribution structure. Tsou et al. teaches attaching a package substrate to the back-side redistribution structure (Paragraph 0066 describes a second redistribution structure, 440, is attached to the package substrate, 200). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to add a package substrate to the back-side redistribution structure, as taught in Tsou et al., because adding a substrate to a redistribution structure can help extend the redistribution structure’s thermal capacity, allowing for better heat spreading and extraction in multi-die packages. Regarding Claim 20, Hsu et al. does not teach that the back-side redistribution structure is formed after the attaching the logic device and the memory device to the front-side redistribution structure. Tsou et al. teaches the back-side redistribution structure being formed after the attaching the logic device and the memory device to the front-side redistribution structure (Fig. 10 shows the logic device, 701, and the memory device, 702, already connected to the front-side redistribution structure, 470. Fig. 14 then shows the back-side redistribution structure, 440, being formed). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to add the back-side redistribution structure after attaching the logic and memory devices to the front-side redistribution structure, as taught in Tsou et al., because forming the back-side redistribution structure after connecting the logic and memory device to the front-side redistribution layer would prevent the back-side redistribution layer from being damaged during the process of forming the rest of the package. Regarding Claim 23, Hsu et al. teaches forming a back-side redistribution structure on a back-side surface of the encapsulant and a back-side surface of the thermal reservoir die (Fig 18 shows a redistribution structure, 150, on the back side surface of the encapsulant, 140’, and the thermal reservoir die, 330), wherein the back-side redistribution structure comprises a dummy metal pattern (In Fig. 14, the metal pattern, 154, is within the back-side redistribution structure, 150), the interconnection die and the thermal reservoir die each overlapping the dummy metal pattern in the plan view (Annotated Fig 18. below shows how the thermal reservoir die, 330, and the interconnection die, 130, PNG media_image2.png 451 750 media_image2.png Greyscale overlaps the dummy metal pattern, 154, in the plan view). Hsu et al. does not teach that the back-side redistribution structure being formed after the attaching the logic device and the memory device to the front-side redistribution structure. Tsou et al. teaches the back-side redistribution structure being formed after the attaching the logic device and the memory device to the front-side redistribution structure (Fig. 10 shows the logic device, 701, and the memory device, 702, already connected to the front-side redistribution structure, 470. Fig. 14 then shows the back-side redistribution structure, 440, being formed). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to add the back-side redistribution structure after attaching the logic and memory devices to the front-side redistribution structure, as taught in Tsou et al., because forming the back-side redistribution structure after connecting the logic and memory device to the front-side redistribution layer would prevent the back-side redistribution layer from being damaged during the process of forming the rest of the package. Regarding Claim 24, Hsu et al. teaches a method comprising: Encapsulating an interconnection die (See the die, 130, in Fig. 18. The die, 130, serves as an interconnection die since it connects to the other dies) and a thermal reservoir die (The dummy dies, 330, in Fig. 18. Paragraph 0040 describes that the dummy dies, 330, serve as heat dissipating elements for the for the package) with an encapsulant (Fig 18 shows the encapsulant, 140’, encapsulating both the interconnection die, 130, and the thermal reservoir die, 330); Forming a front-side redistribution structure over the encapsulant (Paragraph 0049 describes the formation of the front-side redistribution structure, 118. Fig. 18 shows the redistribution structure, 118, formed over the thermal reservoir die, 330, and the encapsulant, 140’); Attaching an integrated circuit device to the front-side redistribution structure (Paragraph 0068 describes the two dies, 220a and 220b as integrated circuits. Paragraph 0072); PNG media_image3.png 451 750 media_image3.png Greyscale Forming a back-side redistribution structure on a back-side of the encapsulant (Fig 18 shows a redistribution structure, 150, on the back side surface of the encapsulant, 140’), the back-side redistribution structure comprising a first dummy metal sheet having first openings, the first dummy metal sheet extending from under the interconnection die to under the thermal reservoir die (The annotated Fig 18 below shows the first metallization sheet extending from under the interconnection device, 130, to under the thermal reservoir die, 330. It also shows the openings in the dummy metal sheet) Hsu et al. does not teach attaching a package substrate to the back-side redistribution structure. Tsou et al. teaches attaching a package substrate to the back-side redistribution structure (Paragraph 0066 describes a second redistribution structure, 440, is attached to the package substrate, 200). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to add a package substrate to the back-side redistribution structure, as taught in Tsou et al., because adding a substrate to a redistribution structure can help extend the redistribution structure’s thermal capacity, allowing for better heat spreading and extraction in multi-die packages. Regarding claim 25, Hsu et al., as modified, lacks specifically the width of the first openings being substantially equal to a length of the first openings. As cited from MPEP 2144.04, in cases where the claim regards a change in size or shape, a prima facie case of obviousness exist. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to have the width and the height of the openings be equal because it allows for better precision while forming the openings, making the process easier and less complex. Regarding Claim 26, Hsu et al., as modified, does not teach each of the first openings having the same width and the same length. As cited from MPEP 2144.04, in Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to make all the openings have the same width and length because uniform dimensions allow for better uniformity, which reduces the chance of misalignment or defects during the etching process. PNG media_image4.png 451 750 media_image4.png Greyscale Regarding claim 27, Hsu et al. as modified, teaches wherein the back-side redistribution structure further comprises a second dummy metal sheet having second openings, the back-side redistribution structure further comprising a functional redistribution line between the first dummy metal sheet and the second dummy metal sheet (The annotated Fig. 18 below shows a second dummy metal sheet, with functional redistribution lines in between the first and second dummy metal sheet). Hsu et al., as modified, does not teach, the second dummy metal sheet extending from under the interconnection die to under the thermal reservoir die. As cited from MPEP 2144.04, in re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to have a second dummy metal sheet extend from under the interconnection die to under the thermal reservoir die because it would increase the lifetime of the device as the second dummy metal sheet would still provide that connection between the two dies if the first was damaged. Regarding claim 28, Hsu et al., as modified, teaches forming a thermal interface material between the thermal reservoir die and the interconnection die (through via 120 is between thermal reservoir die 330 and interconnection die 130, and would broadly offer thermal protection as it acts as a conductive piece between the two structures, so any heat would have to pass through it, therefore, broadly acts as a ‘thermal insulation material’). Regarding claim 29, Hsu et al., as modified, teaches the interconnection die comprising active devices (Paragraph 0029 describes the interconnection die, 130, containing active components) Regarding claim 30, Hsu et al., as modified, teaches planarizing a surface of the encapsulant to be substantially coplanar with a surface of the thermal reservoir die (Paragraph 0046 describes the encapsulation, 140, being planarized. Fig 18 shows the planarized encapsulant, 140’, coplanar with a surface of the thermal reservoir die). Regarding claim 31 Hsu et al. teaches a method comprising: encapsulating an interconnection die (See the die, 130, in Fig. 18. The die, 130, serves as an interconnection die since it connects to the other dies) and a thermal reservoir die (The dummy dies, 330, in Fig. 18. Paragraph 0040 describes that the dummy dies, 330, serve as heat dissipating elements for the for the package) with an encapsulant (Fig 18 shows the encapsulant, 140’, encapsulating both the interconnection die, 130, and the thermal reservoir die, 330); forming a front-side redistribution structure on a front-side surface of the encapsulant and a front-side surface of the thermal reservoir die (Paragraph 0049 describes the formation of the front-side redistribution structure, 118. Fig. 18 shows the redistribution structure, 118, formed on the front side surface of the thermal reservoir die, 330, and the encapsulant, 140’), the front-side redistribution structure comprising first redistribution lines (Figure 18 shows the redistribution lines, 118b, within the front-side redistribution structure, 118); PNG media_image1.png 451 750 media_image1.png Greyscale attaching a logic device and a memory device to the front-side redistribution structure, the first redistribution lines coupling the interconnection die to the logic device and to the memory device (Paragraph 0072 describes the front-side redistribution structure, 118, being directly connected to the joints, 310, which electrically connect to the package, 20, which contains both the logic and memory device. Fig 18 shows the redistribution lines, 118b, directly connected to the joints, 310, which directly connects to the memory and logic device), the thermal reservoir die being confined within edges of the memory device in a plan view (The annotated Fig 18 below shows that the thermal device is confined within the edges of the memory device in plan view), the logic device and the memory device each overlapping the interconnection die in the plan view (The annotated Fig 18 below shows that the memory and logic device both overlap the interconnection die in plan view); PNG media_image5.png 451 750 media_image5.png Greyscale forming a back-side redistribution structure on a back-side surface of the encapsulant and a back-side surface of the thermal reservoir die (Fig 18 shows a redistribution structure, 150, on the back side surface of the encapsulant, 140’, and the thermal reservoir die, 330), the back-side redistribution structure comprising second redistribution lines and a dummy metal sheet, the dummy metal sheet extending from under the interconnection die to under the thermal reservoir die (The annotated Fig. 18 below shows both the second redistribution lines and the dummy metal sheet in the back-side redistribution structure, 150. It also shows the dummy metal sheet extending from under the interconnection die to under the thermal reservoir die); Hsu et al. does not teach attaching a package substrate to the back-side redistribution structure, the second redistribution lines coupling the interconnection die to the package substrate (It does not teach this as the package substrate is yet to be added). Tsou et al. teaches attaching a package substrate to the back-side redistribution structure and the second redistribution lines coupling the interconnection die to the package substrate (Figure 14 shows a package with both a front-side redistribution structure, 470, and a back-side redistribution structure, 440. Paragraph 0066 further describes a second redistribution structure, 440, which corresponds to the back-side redistribution structure, is attached to the package substrate, 200 through the redistribution lines, 444). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to add a package substrate to the back-side redistribution structure, as taught in Tsou et al., because adding a substrate to a redistribution structure can help extend the redistribution structure’s thermal capacity, allowing for better heat spreading and extraction in multi-die packages. PNG media_image3.png 451 750 media_image3.png Greyscale Regarding claim 33, Hsu et al. teaches the dummy metal sheet has a pattern of openings, a first subset of the openings being disposed beneath the interconnection die and a second subset of the openings being disposed beneath the thermal reservoir die (The annotated Fig. 18 below shows the dummy metal sheet having a pattern of openings which appear both beneath the interconnection die and the thermal reservoir die). Regarding Claim 34, Hsu et al. teaches attaching the logic device and the memory device comprising reflowing conductive connectors between the front-side redistribution structure and each of the logic device and the memory device (Paragraph 0072 describes joints, 310, formed from solder balls, which are equivalent to conductive connectors. These joints connect the front-side redistribution structure, 118, to the package, 20, which contains both the memory and logic device. Fig 18 shows these joints, 310, between the front-side redistribution structure, 118, and the memory, 220a, and logic, 220b, device), and the method further comprises forming an underfill around the conductive connectors and between the front-side redistribution structure and each of the logic device and the memory device (Paragraph 0073 describes an underfill, UF, filling the gap between the joints, 310, which are formed of the solder balls, seen labeled in Figure 11. Figure 18 shows it (unlabeled) between the front-side redistribution structure, 118, and the logic device and memory device). Regarding Claim 35, Hsu et al. teaches the dummy metal sheet comprising a via that is in contact with the back-side surface of the thermal reservoir die (Paragraph 0034 describes a conductive pillar, 330d. Fig 18 shows the conductive pillar, 330d, between the dummy metal layer, 154, and the thermal reservoir die, 330). Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20230378152 A1) in view of Lin et al. (US 20230402340 A1). Regarding claim 22, Hsu et al. teaches the thermal reservoir die (330) comprises: a substrate (Paragraph 0034 describes the thermal reservoir die, 330, including a semiconductor substrate, 330s). Hsu et al. does not teach metal features in the substrate, the metal features extending from the front-side surface of the thermal reservoir die to a back-side surface of the thermal reservoir die. Lin et al. teaches the substrate of the thermal reservoir die containing metal features in the substrate, the metal features extending from the front-side surface of the thermal reservoir die to a back-side surface of the thermal reservoir die. (Paragraph 0026 describes thermal silicon substrates, 130, which are also dummy dies, that have copper thermal vias, TV3 that cover the entire vertical length of the die. Fig. 4 shows the metal feature, TV3, in the die, 130, extending from the front side surface of the die to the back side of the surface). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to add a metal feature to the thermal reservoir die substrate that extends from the front-side surface of the thermal reservoir die to the back-side surface of the thermal reservoir die, as taught in Lin et al., because metal has a high thermal conductivity, therefore, adding a metal component to the thermal reservoir die would help the die more effectively transfer heat and distribute it more evenly. Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20230378152 A1) in view of Lin et al. (US 20230402340 A1) as applied to claim 31 above, and further in view of Hsu et al. (US 20190371694 A1). Regarding claim 32, Hsu et al. teaches that the thermal reservoir die is electrically nonfunctional (Paragraph 0027 describes the thermal reservoir die, 330, as a dummy die. It is known in the art that dummy dies are dies that do not contain active circuits such as transistors or diodes). Hsu et al. does not teach that the thermal reservoir die is electrically isolated from the first redistribution lines and from the second redistribution lines. Hsu et al. teaches the thermal reservoir die being electrically isolated from the first and second redistribution lines (Paragraph 0022 states that the dummy die, 140, is electrically floating. Fig 1C shows the dummy die, 140, between the two redistribution structures, RDL1 and RDL2) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu et al. to make the thermal reservoir die electrically isolated from the first and second redistribution lines, as taught in Hsu et al., because decoupling the thermal reservoir die from the redistribution lines because it prevents heat from being dissipated through the electrical pathways of the redistribution structures which protects the electrical performance of the redistribution lines. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Chuang et al. (US 20230343764 A1), Yu et al. (US 11,393,805 B2), and Kuo et al. (US 20220223491 A1) all share a similar structure to the application, containing two redistribution structures, one on the front-side and the other on the back-side of the encapsulant and at least one die. The front-side encapsulant having redistribution lines that connect to a memory device and a logic device. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.E.H./Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Mar 08, 2024
Application Filed
Aug 06, 2026
Non-Final Rejection mailed — §102, §103 (current)

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month