DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 13-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant's arguments filed 2/12/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… no parallel-to-serial and serial-to-parallel circuit …” because Evans’ Figure 5 do not disclose this feature as paragraph [0053] disclose for a read operation sense amplifier bank is not shown and set of output drivers are not shown within the data interface 263 (i.e. Evans does not disclose the above claimed features because sense amplifier bank and set of output drivers are not shown in Figure 5 for read operation); applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, Evans’ Figure 5 teaches/suggests write operation wherein each bit of the write data value is received on a respective data line parallelly via receiving circuits (271) within the write data interface (263) and loaded into respective write driver (2730-273K-1) for forwarding to respective bit lines (272) (Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; and [0151]); therefore, Evans would teach/suggest the above claimed features as data is parallelly communicated (i.e. without parallel-to-serial and serial-to-parallel circuit).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claims 20 and 28, the examiner will also apply the above response for independent claim 1 towards independent claims 20 and 28.
In response to applicant’s arguments with regard to the independent claim 26 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… tracks inside the substrate … does not cross each other …” because paragraph [0052] of PARK discloses “For example, each of the signal lines 231 may be electrically connected to each of other signal lines 231 at a plurality of connection points 232. In addition, at least one of the signal lines 231 may be electrically connected to one of the signal lines 231 disposed on a different laver in the plurality of connection portions 232. For example, in the connection portion 232, among the signal lines 231, a signal line disposed on the layer L1 may be electrically connected to a signal line disposed on the layer L2. a signal line disposed on the layer L2 may be electrically connected to a signal line disposed on the layer L3, and a signal line disposed on the layer L3 may be electrically connected to a signal line disposed on the layer L4, and a signal line disposed on the layer L4 may be electrically connected to a signal line disposed on the layer L1”; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, PARK does teach/suggest the above claimed features as paragraph [0052] of PARK also discloses an alternative embodiment where “… signal lines might not be electrically connected to different signal lines …”.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), Kim et al. (US Pub.: 2005/0249003), and Evans et al. (US Pub.: 2005/0015558).
As per claim 1, Akin teaches/suggests a memory comprising: a memory bank (e.g. associated with memory bank: [0020]); an I/O data bus (e.g. associated with data bus between sense amplifier (38) and processor (40) in Fig. 2); and sensing amplifier (e.g. associated with sense amplifier (38) in Fig. 2) between the memory bank and the I/O data bus, the sensing amplifier configured to operate in parallel; operating with the memory chip (Fig. 2; and [0010]-[0020]).
Akin does not teach the memory chip comprising:
a first plurality of sensing amplifiers, the first plurality of sensing amplifiers configured to output a first plurality of data in parallel to the I/O data bus;
wherein there is no parallel-to-serial circuit and no serial-to-parallel circuit in the memory.
Kim (US Pub.: 2009/0154256) teaches/suggests a system comprising: configured to output a first plurality of data in parallel to the I/O data bus (claim 3; claim 7; Fig. 1-2; [0038]-[0052]; [0057]; and [0060]).
Kim (US Pub.: 2005/0249003) teaches/suggests a system comprising: a first plurality of sensing amplifiers (e.g. associated with IOSA/WDRV (210)-(280) and (310)-(380) in Fig. 4), the first plurality of sensing amplifiers configured to operate accordingly (Fig. 2; Fig. 4; [0018]; and [0033]-[0040]).
Evans teaches/suggests a system comprising: wherein there is no parallel-to-serial circuit and no serial-to-parallel circuit in the memory (e.g. associated with embodiment where data is directly transferred parallelly between data interface (263) and read/write circuit (243) in Fig. 5: Fig. 4-5; [0006]; [0051]) (Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; and [0151]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim’s (US Pub.: 2009/0154256) parallel bus architecture, Kim’s (US Pub.: 2005/0249003) sense amplifier bus architecture and Evans’ data transferring architecture into Akin’s memory chip for the benefit of reducing detrimental impact (Kim (US Pub.: 2009/0154256), [0047]), providing high-speed data transfer while decreasing cell area (Kim (US Pub.: 2005/0249003), [0024]), and saving bandwidth (Evans, [0040]-[0041]) to obtain the invention as specified in claim 1.
As per claim 6, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans teach/suggest all the claimed features of claim 1 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans further teach/suggest the memory chip of comprising wherein a width of the I/O data bus is equal to a width of the first plurality of data parallelly outputted by the first plurality of sensing amplifiers (e.g. associated with data being outputted via DQ-1 to DQ-n in Fig. 1 of Kim (US Pub.: 2009/0154256)) (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]).
As per claim 7, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans teach/suggest all the claimed features of claim 1 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans further teach/suggest the memory chip of further comprising a plurality of transceivers between the first plurality of sensing amplifiers and the I/O data bus, wherein the plurality of transceivers parallelly receive and transmit the first plurality of data from the first plurality of sensing amplifiers to the I/O data bus (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]).
As per claim 8, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans teach/suggest all the claimed features of claim 7 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans further teach/suggest the memory chip of further comprising a second plurality of sensing amplifiers between the memory bank and the first plurality of sensing amplifiers, wherein the second plurality of sensing amplifiers comprise M sensing amplifiers and are connected to bit lines of the memory chip, the first plurality of sensing amplifiers comprise N sensing amplifiers and are connected to data lines of the memory chip, both N and M are positive integers, and M is not less than N (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features as data is parallelly communicated with the memory banks.
As per claim 9, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans teach/suggest all the claimed features of claim 8 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans further teach/suggest the memory chip of comprising wherein a portion of the second plurality of sensing amplifiers are selectively coupled to the first plurality of sensing amplifiers, and the portion of the second plurality of sensing amplifiers parallelly output the first plurality of data to the first plurality of sensing amplifiers; wherein a number of sensing amplifiers in the portion of the second plurality of sensing amplifiers is equal to N (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features as data is parallelly communicated with the memory banks.
As per claim 10, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans teach/suggest all the claimed features of claim 9 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans further teach/suggest the memory chip of comprising wherein the portion of the second plurality of sensing amplifiers are selectively coupled to the first plurality of sensing amplifiers according to a control signal inputted to the memory chip (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features as data is parallelly communicated with the memory banks.
As per claim 11, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans teach/suggest all the claimed features of claim 10 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans further teach/suggest the memory chip of comprising wherein the control signal includes a plurality of signal bits configured to be stored in a register of the memory chip (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features as data is parallelly communicated with the memory banks.
As per claim 12, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans teach/suggest all the claimed features of claim 10 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans further teach/suggest the memory chip of further comprising a plurality of bit switches between the first plurality of sensing amplifiers and the second plurality of sensing amplifiers, wherein the plurality of bit switches electrically connect to the portion of the second plurality of sensing amplifiers and the first plurality of sensing amplifiers according to the control signal (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features as data is parallelly communicated with the memory banks
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), Kim et al. (US Pub.: 2005/0249003), and Evans et al. (US Pub.: 2005/0015558) as applied to claim 1 above, and further in view of Kim et al. (US Pub.: 2022/0139448).
As per claim 2, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans teach/suggest all the claimed features of claim 1 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans further teach/suggest the memory chip comprising wherein the memory chip communicates as the memory chip operate accordingly (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), but Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans does not teach sends out a handshaking signal to selectively notice whether memory module does not execute a refresh operation.
Kim (US Pub.: 2022/0139448) teaches/suggest a system comprising sends out a handshaking signal to selectively notice whether memory module does not execute a refresh operation (e.g. associated with selective sending no-self-refresh operation signal/ self-refresh operation signal: [0029]-[0031]) (Fig. 1; [0010]-[0012]; and [0029]-[0033]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim (US Pub.: 2022/0139448)’s selective signaling into Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), and Evans’ memory chip for the benefit of improving performance and reliability (Kim (US Pub.: 2022/0139448), [0017]) to obtain the invention as specified in claim 2.
As per claim 3, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, and Kim (US Pub.: 2022/0139448) teach/suggest all the claimed features of claim 2 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, and Kim (US Pub.: 2022/0139448) the memory chip further comprising an extra output pin, wherein the handshaking signal is sent to a memory controller through the extra output pin, wherein the memory controller is physically separate from the memory chip (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]).
As per claim 4, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, and Kim (US Pub.: 2022/0139448) teach/suggest all the claimed features of claim 2 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, and Kim (US Pub.: 2022/0139448) the memory chip further comprising a refresh counter, wherein the handshaking signal is selectively active according to number of clocks counted by the refresh counter (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]), wherein it would have been obvious to one ordinary skilled in the art to further include the above claimed features.
As per claim 5, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, and Kim (US Pub.: 2022/0139448) teach/suggest all the claimed features of claim 2 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, and Kim (US Pub.: 2022/0139448) the memory chip further comprising wherein the handshaking signal is active when the memory chip is executing the refresh operation, and the handshaking signal is non-active when the memory chip does not execute the refresh operation (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]).
Claims 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), Kim et al. (US Pub.: 2005/0249003), Evans et al. (US Pub.: 2005/0015558), Kim et al. (US Pub.: 2022/0139448), and Arimoto et al. (US Pub.: 2002/0159318).
As per claim 13, Akin teaches/suggests a memory comprising: a plurality of memory banks (e.g. associated with memory banks: [0020]); data lines (e.g. associated with corresponding data lines for the memory arrays); sensing amplifier (e.g. associated with sense amplifier (38) in Fig. 2) coupled to the data lines, wherein the sensing amplifier is corresponding to one of the plurality of memory banks and is configured to parallelly operate (e.g. associated with communication between memory (14) and sense amplifier (38) in Fig. 2); and an I/O data bus (e.g. associated with data bus between sense amplifier (38) and processor (40) in Fig. 2); and operating with the memory chip, and when the memory chip communicates as the memory chip operate accordingly, accesses the memory chip as the memory chip operate accordingly, wherein operating accordingly with the memory chip (e.g. associated with communication among memory (14), sense amplifier (38) and SSN processor (40) in Fig. 2) (Fig. 2; and [0010]-[0020]).
Akin does not teach the memory chip comprising:
a plurality set of sensing amplifiers, wherein each set of sensing amplifiers is operating accordingly and is configured to parallelly output a plurality of data; and
wherein there is no parallel-to-serial circuit and no serial-to-parallel circuit in the memory, and
sends out a handshaking signal during a present R/W time corresponding to a current access command to selectively notice a memory controller that the memory prepares to execute a refresh operation, the memory controller continues to accesses the memory according to the current access command but withholds a next access command to the memory until the handshaking signal is deactivated, wherein the current access command and the next access command are used to read data from or write data to the memory.
Kim (US Pub.: 2009/0154256) teaches/suggests a system comprising: being configured to parallelly output a plurality of data (claim 3; claim 7; Fig. 1; [0044]; [0052]; [0057]); and operating with a memory controller (Fig. 1, ref. 101), wherein the memory controller operate (Fig. 1, ref. 101) accordingly (claim 3; claim 7; Fig. 1-2; [0038]-[0052]; [0057]; [0060]; and [0066]).
Kim (US Pub.: 2005/0249003) teaches/suggests a system comprising: a plurality set of sensing amplifiers (e.g. associated with bit line sense amplifying units, IOSA/WDRV (210)-(280), and (310)-(380) in Fig. 4), wherein each set of sensing amplifiers is operating accordingly (Fig. 2; Fig. 4; [0018]; and [0033]-[0040]).
Evans teaches/suggests a system comprising: wherein there is no parallel-to-serial circuit and no serial-to-parallel circuit in the memory (e.g. associated with embodiment where data is directly transferred parallelly between data interface (263) and read/write circuit (243) in Fig. 5: Fig. 4-5; [0006]; [0051]) (Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; and [0151]).
Kim (US Pub.: 2022/0139448) teaches/suggest a system comprising: sends out a handshaking signal to selectively notice that the memory is operating accordingly (e.g. associated with selective sending no-self-refresh operation signal/self-refresh operation signal: [0029]-[0031]), operating accordingly but withholds a next access command to the memory until the handshaking signal is deactivated (Fig. 1; [0010]-[0012]; and [0029]-[0033]).
Arimoto teaches/suggest a system comprising: during a present R/W time corresponding to a current access command prepares to execute a refresh operation, continues to accesses the memory according to the current access command, wherein the current access command and the next access command are used to read data from or write data to the memory (e.g. associated refresh request after memory access request, wherein the refresh request is deferred until completion of the read/write operation: [0042]; and [0169]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim’s (US Pub.: 2009/0154256) parallel bus architecture, Kim’s (US Pub.: 2005/0249003) sense amplifier bus architecture, Evans’ data transferring architecture, Kim (US Pub.: 2022/0139448)’s selective signaling, and Arimoto’s refresh operations into Akin’s memory chip for the benefit of reducing detrimental impact (Kim (US Pub.: 2009/0154256), [0047]), providing high-speed data transfer while decreasing cell area (Kim (US Pub.: 2005/0249003), [0024]), saving bandwidth (Evans, [0040]-[0041]), improving performance and reliability (Kim (US Pub.: 2022/0139448), [0017]), and implementing a simple control signal for refresh operations (Arimoto, [0042]) to obtain the invention as specified in claim 13.
As per claim 14, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto teach/suggest all the claimed features of claim 13 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto the memory chip further comprising an extra output pin, wherein the handshaking signal is sent to the memory controller through the extra output pin, wherein the memory controller is physically separate from the memory chip (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; and Arimoto, [0042]; [0169]).
As per claim 15, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto teach/suggest all the claimed features of claim 13 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto the memory chip comprising wherein the handshaking signal is active when the memory chip is executing the refresh operation, and the handshaking signal is non-active when the memory chip does not execute the refresh operation (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; and Arimoto, [0042]; [0169]).
As per claim 16, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto teach/suggest all the claimed features of claim 15 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto the memory chip further comprising a refresh counter, wherein the handshaking signal is selectively active according to number of clocks counted by the refresh counter (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]; and Arimoto, [0042]; [0169]), wherein it would have been obvious to one ordinary skilled in the art to further include the above claimed features.
As per claim 17, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto teach/suggest all the claimed features of claim 13 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto the memory chip comprising wherein: the plurality of memory banks comprise a first memory bank and a second memory bank; the plurality set of sensing amplifiers comprise a first set of sensing amplifiers coupled to the data lines and a second set of sensing amplifiers coupled to the data lines; the first set of sensing amplifiers are corresponding to the first memory bank and configured to parallelly output a first plurality of data, and the second set of sensing amplifiers are corresponding to the second memory bank and configured to parallelly output a second plurality of data; and a width of the I/O data bus is equal to the sum of a width of the first plurality of data and a width of the second plurality of data (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]; and Arimoto, [0042]; [0169]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features as data is parallelly communicated with the memory banks.
As per claim 18, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto teach/suggest all the claimed features of claim 17 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto the memory chip further comprising: bit lines; a third set of sensing amplifiers coupled to the bit lines and configured between the first memory bank and the first set of sensing amplifiers; and a fourth set of sensing amplifiers coupled to the bit lines and configured between the second memory bank and the second set of sensing amplifiers; wherein a portion of the third set of sensing amplifiers are selectively coupled to the first set of sensing amplifiers, and a number of sensing amplifiers in the portion of the third set of sensing amplifiers is equal to a number of sensing amplifiers in the first set of sensing amplifiers; wherein a portion of the fourth set of sensing amplifiers are selectively coupled to the second set of sensing amplifiers, and a number of sensing amplifiers in the portion of the fourth set of sensing amplifiers is equal to a number of sensing amplifiers in the second set of sensing amplifiers (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]; and Arimoto, [0042]; [0169]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features as data is parallelly communicated with the memory banks.
As per claim 19, Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto teach/suggest all the claimed features of claim 18 above, where Akin, Kim (US Pub.: 2009/0154256), Kim (US Pub.: 2005/0249003), Evans, Kim (US Pub.: 2022/0139448), and Arimoto the memory chip comprising wherein the portion of the third set of sensing amplifiers are selectively coupled to the first set of sensing amplifiers according to a control signal inputted to the memory chip, and the portion of the fourth set of sensing amplifiers are selectively coupled to the second set of sensing amplifiers according to the control signal (Akin, Fig. 2; [0010]-[0020]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-3; [0038]-[0052]; [0057]; [0060]; Kim (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0018]; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]; and Arimoto, [0042]; [0169]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features as data is parallelly communicated with the memory banks.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), and Evans et al. (US Pub.: 2005/0015558).
As per claim 20, Akin teaches/suggests a memory controller for a DRAM system, the DRAM system comprising a system bus interface and a memory chip, the memory chip comprising an I/O data bus, the memory controller comprising: a control circuit (e.g. associated with memory controller) configured to couple to the system bus interface (e.g. associated with interface for data transferring with memory array); and being coupled to the control circuit and configured to operate with the I/O data bus of the memory chip; operating with circuitry of the memory controller (Fig. 2; [0010]-[0020]; [0029]; and [0032]).
Akin does not teach the memory controller comprising:
a physical layer circuit to parallelly receive a first plurality of data from bus;
wherein there is no serial-to-parallel circuit and no parallel-to-serial circuit in the physical layer circuit.
Kim (US Pub.: 2009/0154256) teaches/suggests a system comprising: a physical layer circuit to parallelly receive a first plurality of data from bus; and operating with circuit in the physical layer circuit (claim 3; claim 7; Fig. 1-2; [0038]-[0052]; [0057]; and [0060]).
Evans teaches/suggests a system comprising: wherein there is no serial-to-parallel circuit and no parallel-to-serial circuit (e.g. associated with embodiment where data is directly transferred parallelly between data interface (263) and read/write circuit (243) in Fig. 5: Fig. 4-5; [0006]; [0051]) (Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; and [0151]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim’s (US Pub.: 2009/0154256) parallel bus architecture, and Evans’ data transferring architecture into Akin’s memory chip for the benefit of reducing detrimental impact (Kim (US Pub.: 2009/0154256), [0047]), and saving bandwidth (Evans, [0040]-[0041]) to obtain the invention as specified in claim 20.
As per claim 21, Akin, Kim (US Pub.: 2009/0154256), and Evans teach/suggest all the claimed features of claim 20 above, where Akin, Kim (US Pub.: 2009/0154256), and Evans further teach/suggest the memory controller comprising wherein the physical layer circuit is further configured to parallelly output a second plurality of data to the I/O data bus of the memory chip (e.g. associated with parallelly communication with memory) (Akin, Fig. 2; [0010]-[0020]; [0029]; [0032]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-2; [0038]-[0052]; [0057]; [0060]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]).
Claims 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), and Evans et al. (US Pub.: 2005/0015558) as applied to claim 20 above, and further in view of Kim et al. (US Pub.: 2022/0139448).
As per claim 22, Akin, Kim (US Pub.: 2009/0154256), and Evans teach/suggest all the claimed features of claim 18 above, where Akin, Kim (US Pub.: 2009/0154256), and Evans further teach/suggest the memory controller comprising wherein the memory controller receives communication from the memory chip for operating the memory controller whether the memory chip communicates (Akin, Fig. 2; [0010]-[0020]; [0029]; [0032]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-2; [0038]-[0052]; [0057]; [0060]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), but Akin, Kim (US Pub.: 2009/0154256), and Evans do not teach communicating a handshaking signal to selectively notice whether memory module does not execute a refresh operation.
Kim (US Pub.: 2022/0139448) teaches/suggest a system comprising communicating a handshaking signal to selectively notice whether memory module does not execute a refresh operation (e.g. associated with selective sending no-self-refresh operation signal/ self-refresh operation signal: [0029]-[0031]) (Fig. 1; [0010]-[0012]; and [0029]-[0033]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim (US Pub.: 2022/0139448)’s selective signaling into Akin, Kim (US Pub.: 2009/0154256), and Evans’ memory chip for the benefit of improving performance and reliability (Kim (US Pub.: 2022/0139448), [0017]) to obtain the invention as specified in claim 22.
As per claim 23, Akin, Kim (US Pub.: 2009/0154256), Evans, and Kim (US Pub.: 2022/0139448) teach/suggest all the claimed features of claim 22 above, where Akin, Kim (US Pub.: 2009/0154256), Evans, and Kim (US Pub.: 2022/0139448) further teach/suggest the memory controller comprising wherein the handshaking signal is active when the memory chip is executing the refresh operation, and the handshaking signal is non-active when the memory chip does not execute the refresh operation (Akin, Fig. 2; [0010]-[0020]; [0029]; [0032]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-2; [0038]-[0052]; [0057]; [0060]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]).
As per claim 24, Akin, Kim (US Pub.: 2009/0154256), Evans, and Kim (US Pub.: 2022/0139448) teach/suggest all the claimed features of claim 23 above, where Akin, Kim (US Pub.: 2009/0154256), Evans, and Kim (US Pub.: 2022/0139448) further teach/suggest the memory controller comprising wherein when the handshaking signal is active, the memory controller holds an access command which is intended to read data from or write data to the memory chip (Akin, Fig. 2; [0010]-[0020]; [0029]; [0032]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-2; [0038]-[0052]; [0057]; [0060]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]).
As per claim 25, Akin, Kim (US Pub.: 2009/0154256), Evans, and Kim (US Pub.: 2022/0139448) teach/suggest all the claimed features of claim 24 above, where Akin, Kim (US Pub.: 2009/0154256), Evans, and Kim (US Pub.: 2022/0139448) further teach/suggest the memory controller comprising wherein the memory controller sends the held access command to the memory chip after the handshaking signal is non-active (Akin, Fig. 2; [0010]-[0020]; [0029]; [0032]; Kim (US Pub.: 2009/0154256), claim 3; claim 7; Fig. 1-2; [0038]-[0052]; [0057]; [0060]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim (US Pub.: 2022/0139448), Fig. 1; [0010]-[0012]; [0029]-[0033]; [0042]).
Claims 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Evans et al. (US Pub.: 2005/0015558) and PARK et al. (US Pub.: 2025/0062239).
As per claim 26, Akin teaches/suggests a memory system comprising: a system bus interface (e.g. associated with interface for data transferring with memory chip); a memory controller, wherein the memory controller is coupled to the system bus interface, the memory controller further comprises a physical layer, and operating with the physical layer of the memory controller; a memory chip, wherein the memory chip is coupled to the memory controller, operating with the memory chip; and wherein the memory controller and the memory chip are operating accordingly (Fig. 2; Fig. 5; [0010]-[0020]; and [0029]-[0032]).
Akin does not teach the memory system comprising:
with a controller I/O data bus coupled to a plurality of second bump groups, and there is no parallel-to-serial circuit and no serial-to-parallel circuit in architecture;
with a memory I/O data bus coupled to a plurality of first bump groups, there is no parallel-to-serial and no serial-to-parallel circuit in architecture; and
a substrate, modules disposed on the substrate and horizontally space apart from each other, and tracks inside the substrate connected the plurality of first bumps groups to the plurality of the second bump groups do not cross each other.
Evans teaches/suggests a system comprising: there is no parallel-to-serial circuit and no serial-to-parallel circuit in architecture; and there is no parallel-to-serial and no serial-to-parallel circuit in architecture (e.g. associated with embodiment where data is directly transferred parallelly between data interface (263) and read/write circuit (243) in Fig. 5: Fig. 4-5; [0006]; [0051]) (Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; and [0151]).
PARK teaches/suggests a system comprising:
with a controller I/O data bus coupled to a plurality of second bump groups (e.g. associated with bumps (221) for coupling to corresponding bus of memory controller (220) in Fig. 2: [0044]);
with a memory I/O data bus coupled to a plurality of first bump groups (e.g. associated with bumps (215) for coupling to corresponding bus of memory device (210) in Fig. 2: [0042]); and
a substrate (e.g. associated with Fig. 2, ref. 230), modules disposed on the substrate and horizontally space apart from each other (e.g. associated with memory device (210) and memory controller (220) being on interposer (230) in Fig. 2: [0039]-[0044]), and tracks inside the substrate connected the plurality of first bumps groups to the plurality of the second bump groups do not cross each other (i.e. as referenced in applicant’s remarks that paragraph [0052] of PARK also discloses “… signal lines might not be electrically connected to different signal lines …”) (claims 1-2; claim 15; Fig. 1-2; [0031]; and [0038]-[0045]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Evans’ data transferring architecture, and PARK’s substrate architecture into Akin’s memory system for the benefit of saving bandwidth (Evans, [0040]-[0041]), and increasing data throughput (PARK, [0031]) to obtain the invention as specified in claim 26.
As per claim 27, Akin, Evans, and PARK teach/suggest all the claimed features of claim 26 above, where Akin, Evans, and PARK further teach/suggest the memory system comprising wherein the plurality of first bump groups are arranged in side-by-side order, the plurality of second bump groups are arranged in side-by-side, and each bump group of the plurality of first bump groups is connected to a corresponding bump group of the plurality of second bump groups through a corresponding track inside the substrate (Fig.res 1-2 of PARK)(Akin, Fig. 2; Fig. 5; [0010]-[0020]; [0029]-[0032]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and PARK, claims 1-2; claim 15; Fig. 1-2; [0031]; [0038]-[0045]).
Claims 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), Sohn et al. (US Pub.: 2005/0071582), and Evans et al. (US Pub.: 2005/0015558).
As per claim 28, Akin teaches/suggests a memory chip comprising: a first set of memory banks (e.g. associated with DRAM bank: [0020]); and an I/O data bus (e.g. associated with input / output data bus for memory array for transferring data with the memory array) of the memory chip electrically coupled to the first set of memory banks, wherein each memory bank transmits to the I/O data bus, operating with the I/O data bus with data of each memory bank of the first set of the memory banks, operating with the memory chip (Fig. 2; Fig. 5; [0010]-[0020]; and [0029]-[0032]).
Akin does not teach the memory chip comprising: transmits a first predetermined width of data to bus in parallel, a width of bus is equal to a sum of the first predetermined width of data, and the first predetermined width is programmable according to a set of control signals; wherein there is no parallel-to-serial and no serial-to-parallel circuit in memory.
Kim teaches/suggests a system comprising: transmits a first predetermined width of data to bus in parallel (e.g. associated with parallel transmitting data via DQ-1 to DQ-n having corresponding predetermined width in Fig. 1), a width of bus is equal to a sum of the first predetermined width of data (e.g. associated with equally transmitting data via DQ-1 to DQ-n having corresponding predetermined width parallelly in Fig. 1) (Fig. 1-3; and [0038]-[0050]).
Sohn teaches/suggests a system comprising: the first predetermined width is programmable according to a set of control signals (e.g. associated with controlling data width for read/write operation) (Fig. 4; [0036]; [0040]; and [0054]-[0056]).
Evans teaches/suggests a system comprising: wherein there is no parallel-to-serial and no serial-to-parallel circuit in memory (e.g. associated with embodiment where data is directly transferred parallelly between data interface (263) and read/write circuit (243) in Fig. 5: Fig. 4-5; [0006]; [0051]) (Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; and [0151]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim’s parallel bus architecture, Sohn’s dynamic width controlling and Evans’ data transferring architecture into Akin’s memory chip for the benefit of reducing detrimental impact (Kim, [0047]), enabling varying data width on the fly during memory operations (Sohn, [0030]), and saving bandwidth (Evans, [0040]-[0041]) to obtain the invention as specified in claim 28.
As per claim 29, Akin, Kim, Sohn and Evans teach/suggest all the claimed features of claim 28 above, where Akin, Kim, Sohn and Evans further teach/suggest the memory chip further comprising: a second set of memory banks, wherein each memory bank of the second set of memory banks transmits a second predetermined width of data to the I/O data bus in parallel, the width of the I/O data bus is selectively equal to, based on a selection signal, the sum of the first predetermined width of data of each memory bank of the first set of the memory banks or a sum of the second predetermined width of data of each memory bank of the second set of the memory banks (Akin, Kim and Sohn Akin, Fig. 2; Fig. 5; [0010]-[0020]; [0029]-[0032]; Kim, Fig. 1-3; [0038]-[0050]; and Sohn, Fig. 4; [0036]; [0040]; [0054]-[0056]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for the subsequent data transferring with corresponding banks.
As per claim 30, Akin, Kim, Sohn and Evans teach/suggest all the claimed features of claim 29 above, where Akin, Kim, Sohn and Evans further teach/suggest the memory chip further comprising: wherein when the width of the I/O data bus is equal to the sum of the second predetermined width of data of each memory bank of the second set of the memory banks, the second predetermined width is programmable according to the set of control signals (Akin, Fig. 2; Fig. 5; [0010]-[0020]; [0029]-[0032]; Kim, Fig. 1-3; [0038]-[0050]; and Sohn, Fig. 4; [0036]; [0040]; [0054]-[0056]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for the subsequent data transferring with corresponding banks.
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 April 08, 2026
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