Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 05/06/2026. Currently, claims 1-13 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Species I (Figures 1-3), claims 1-13, in the reply filed on 05/06/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7-8 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHOI et al (US 20220077064 A1).
Regarding claim 1, Figure 7 of CHOI discloses a package structure, comprising:
at least one semiconductor device (202, [0024]);
at least one inactive element (231, [0100]) disposed around the at least one semiconductor device, and including a main portion and at least one through via (235, [0100]) extending through the main portion; and
an encapsulant (233, [0100]) encapsulating the at least one semiconductor device and the at least one inactive element, wherein a first surface (top surface) of the encapsulant (233) is substantially coplanar with a first surface (top surface) of the at least one inactive element (231) and a first surface (top surface) of the at least one semiconductor device (202), and a second surface (bottom surface) of the encapsulant (233) is substantially coplanar with a second surface (bottom surface) of the at least one inactive element (231) and a second surface (bottom surface) of the at least one semiconductor device (202).
Regarding claim 2, Figure 7 of CHOI discloses that the package structure of claim 1, wherein a width (lateral) of the at least one semiconductor device (202) is greater than a width of the at least one inactive element (231).
Regarding claim 7, Figure 7 of CHOI discloses that the package structure of claim 1, wherein the at least one inactive element (231) does not include a horizontal conduction path on the main portion of the at least one inactive element (231, [0100]).
Regarding claim 8, Figure 7 of CHOI discloses that the package structure of claim 1, wherein a first surface (top surface) of the at least one through via (235, [0100]) of the at least one inactive element is exposed from the first surface of the at least one inactive element (231), and a second surface (bottom surface) of the at least one through via of the at least one inactive element is exposed from the second surface of the at least one inactive element.
Regarding claim 11, Figure 7 of CHOI discloses that the package structure of claim 1, further comprising: a redistribution structure (240, [0098]) disposed on the first surface (top surface) of the encapsulant (233), the first surface of the at least one inactive element and the first surface of the at least one semiconductor device, and electrically connected to the at least one semiconductor device (202) and the at least one through via (235) of the at least one inactive element (231).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being obvious over Brun et al (US 20230074181 A1) in view of Elsherbini et al (US 20200091128 A1).
Regarding claim 1, Figure 1 of Brun discloses a package structure, comprising:
at least one semiconductor device (106B, [0032]);
at least one inactive element (106A, [0032] and [0034], considering die with passive circuits only) disposed around the at least one semiconductor device, and including a main portion (upper portion of 106A in the Figure 1) and at least one through via (vertical connection line in 106A) extending through the main portion; and
an encapsulant (108, [033]) encapsulating the at least one semiconductor device (106B) and the at least one inactive element (106A).
Brun does not teach wherein a first surface (top surface) of the encapsulant (108) is substantially coplanar with a first surface of the at least one inactive element (106A) and a first surface of the at least one semiconductor device (106B), and a second surface (bottom surface) of the encapsulant is substantially coplanar with a second surface of the at least one inactive element and a second surface of the at least one semiconductor device.
However, Elsherbini is a pertinent art which teaches a package substrate for mechanical stability and to facilitate connection to other components. Figure 1 of Elsherbini teaches such a package wherein a top surface and bottom surface of a encapsulating material in a first layer 104-1 ([0023]) are coplanar with a top surface and a bottom surface a semiconductor devices (114-21 and 114-2) as well as the vias around the devices in a method of forming high density microelectronic assemblies ([0033]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Brun such that a first surface (top surface) of the encapsulant (108, Figure 1 of Brun) is substantially coplanar with a first surface of the at least one inactive element (106A) and a first surface of the at least one semiconductor device (106B), and a second surface (bottom surface) of the encapsulant is substantially coplanar with a second surface of the at least one inactive element and a second surface of the at least one semiconductor device according to the teaching of Elsherbini in order to form device with high density microelectronic assemblies with less area and lower cost ([0033], Elsherbini).
Regarding claim 2, Figure 1 of Brun does not teach that the package structure of claim 1, wherein a width of the at least one semiconductor device (106B) is greater than a width of the at least one inactive element (106A).
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to minimize the device size and high integrity with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 3, Figure 1 of Brun discloses that the package structure of claim 1, wherein the at least one semiconductor device (106B, [0032]) include a main portion and an active circuit structure disposed on the main portion, wherein a thickness of the main portion of the at least one semiconductor device is less than a thickness of the main portion of the at least one inactive element (considering a smaller thickness at the top side of the device 106B as the main portion having a circuit with the connecting pads meets the limitation on a broadest reasonable interpretation since the claim does not recites limitation specific to the active circuit structure).
Regarding claim 4, Figure 1 of Brun discloses that the package structure of claim 3, wherein a material of the main portion of the at least one semiconductor device (106B) is same as a material of the main portion of the at least one inactive element (106A) (based on the Figure).
Regarding claim 5, Figure 1 of Brun discloses that the package structure of claim 3, wherein the active circuit structure (106B) includes at least one pad (connections at the top surface of the die 106B) exposed from the first surface (top surface) of the at least one semiconductor device.
Regarding claim 6, Figure 1 of Brun discloses that the package structure of claim 3, wherein the at least one semiconductor device (106B) does not include a vertical conduction path in the main portion of the at least one semiconductor device (no via in 106B based on the Figure).
Regarding claim 7, Figure 1 of Brun discloses that the package structure of claim 1, wherein the at least one inactive element (106A) does not include a horizontal conduction path on the main portion of the at least one inactive element.
Regarding claim 8, Figure 1 of Brun discloses that the package structure of claim 1, wherein a first surface (top surface) of the at least one through via (vertical lines within 106A are the vias and exposed at the top surface of 106A) of the at least one inactive element is exposed from the first surface of the at least one inactive element, and a second surface (bottom surface) of the at least one through via of the at least one inactive element (vertical lines within 106A are the vias and exposed at the bottom surface of 106A) is exposed from the second surface of the at least one inactive element.
Regarding claim 9, Figure 1 of Brun discloses that the package structure of claim 1, wherein the at least one inactive element includes a first inactive element (106A, left one) and a second inactive element (106A, right one) disposed around the first semiconductor device and the second semiconductor device.
Brun does not explicitly teach wherein the at least one semiconductor device includes a first semiconductor device and a second semiconductor device disposed side by side.
However, Brun teaches that a particular number and arrangement of structures and components are presented for illustrative purposes and any desired number or arrangement of such structures and components may be present in various embodiments. Further, the structures shown in the figures may take any suitable form or shape according to material properties, fabrication processes, and operating conditions ([0027]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Brun in view of Elsherbini wherein the at least one semiconductor device includes a first semiconductor device and a second semiconductor device disposed side by side in order to increase the functionality of the package according to the teaching of Adan, since the court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 10, Figure 1 of Brun discloses that the package structure of claim 9, wherein the encapsulant (108) is disposed in a space between the first semiconductor device and the first inactive element, a space between the first semiconductor device and the second semiconductor device, and a space between the second semiconductor device and the second inactive element (Figure 1 teaches that each of the devices are separated by the encapsulant 108).
Regarding claim 11, Figure 1 of Brun discloses that the package structure of claim 1, further comprising: a redistribution structure (layer between 108 and 130) disposed on the first surface of the encapsulant (108), the first surface of the at least one inactive element (106A) and the first surface of the at least one semiconductor device (106B), and electrically connected to the at least one semiconductor device and the at least one through via of the at least one inactive element.
Regarding claim 12, Figure 1 of Brun discloses that the package structure of package structure of claim 1, further comprising: an upper electronic device (130, [0037], considering dies 102 including the molding is an electronic device on a broadest reasonable interpretation) disposed over the first surface of the encapsulant (108), the first surface of the at least one inactive element (106A) and the first surface of the at least one semiconductor device (106B), and electrically connected to the at least one semiconductor device and the at least one through via of the at least one inactive element (106A).
Regarding claim 13, Figure 1 of Brun discloses that the package structure of claim 12, wherein a lateral surface of the upper electronic device (130, [0037]) is substantially aligned with a lateral surface of the encapsulant (108).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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