Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 08/06/2026. Currently, claims 1-13 are pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8 and 11 are rejected under 35 U.S.C. 103 as being obvious over CHOI et al (US 20220077064 A1) in view of LI et al (US 20250062285 A1).
Regarding claim 1, Figure 7 of CHOI discloses a package structure, comprising:
at least one semiconductor device (202, [0024]);
at least one inactive element (231, [0100]) disposed around the at least one semiconductor device, and including a main portion and at least one through via (235, [0100]) extending through the main portion; and
an encapsulant (233, [0100]) encapsulating the at least one semiconductor device and the at least one inactive element, wherein a first surface (top surface) of the encapsulant (233) is substantially coplanar with a first surface (top surface) of the at least one inactive element (231) and a first surface (top surface) of the at least one semiconductor device (202), and a second surface (bottom surface) of the encapsulant (233) is substantially coplanar with a second surface (bottom surface) of the at least one inactive element (231) and a second surface (bottom surface) of the at least one semiconductor device (202).
CHOI does not explicitly teach wherein the at least one semiconductor device comprises: a main portion, wherein the second surface of the at least one semiconductor device is defined at a bottom surface of the main portion, such that the bottom surface of the main portion is coplanar with the second surface of the encapsulant and the second surface of the at least one inactive element; an active circuit structure disposed on the main portion, wherein the top surface of the at least one semiconductor device is defined at a top surface of the active circuit structure, such that the top surface of the active circuit structure is coplanar with the first surface of the encapsulant and the first surface of the at least one inactive element; and at least a pad embedded in the active circuit structure from the top surface thereof, wherein the pad is exposed from the top surface of the active circuit structure, such that a top surface of the pad, the first surface of the encapsulant, and the first surface of the at least one inactive element are coplanar.
However, LI is a pertinent art which teaches a semiconductor package that use a face-to-face stacked die configuration (Figure 1) to achieve various IC design goals. In this context, a “face” of a die refers to the surface of the die adjacent to an active region of the die that includes active circuitry. For example, the active region can include various layers and structures that define circuit elements, such as transistors, conductors, passive circuit elements (e.g., resistors, inductors, capacitors, etc.). In this example, the face of the die corresponds to the side of the die that bounds this active region. In contrast, a “back” of the die refers to an opposite side of the die which bounds an inactive region of the die. For example, the inactive region typically includes undoped monocrystalline semiconductive material and other inactive layers (e.g., passivation layers) ([0020]). LI further teaches that such arrangement improves performance, shorter signal path and cost ([0023]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of CHOI as claimed above according to the teaching of LI in order to improve performance and shorten signal path and lower cost ([0023] of LI).
Regarding claim 2, Figure 7 of CHOI discloses that the package structure of claim 1, wherein a width (lateral) of the at least one semiconductor device (202) is greater than a width of the at least one inactive element (231).
Regarding claim 3, Figure 7 of CHOI in view of LI teaches that the package structure of Claim 1, wherein a thickness of the main portion of the at least one semiconductor device (202) is less than a thickness of the main portion of the at least one inactive element (231) (please see Figure 1 of LI wherein the main portion is having less thickness).
Regarding claim 7, Figure 7 of CHOI discloses that the package structure of claim 1, wherein the at least one inactive element (231) does not include a horizontal conduction path on the main portion of the at least one inactive element (231, [0100]).
Regarding claim 8, Figure 7 of CHOI in view of LI teaches that the package structure of claim 1, wherein a first surface (top surface) of the at least one through via (235, [0100]) of the at least one inactive element is exposed from the first surface of the at least one inactive element (231), and a second surface (bottom surface) of the at least one through via of the at least one inactive element is exposed from the second surface of the at least one inactive element, wherein the first surface of the at least one through via is coplanar with the first surface of the encapsulant and the top surface of the active circuit structure of the at least one semiconductor device; wherein the second surface of the at least one through via is coplanar with the second surface of the encapsulant and the top surface of the bottom surface of the main portion of the at least one semiconductor device.
Regarding claim 11, Figure 7 of CHOI discloses that the package structure of claim 1, further comprising: a redistribution structure (240, [0098]) which comprises: a dielectric layer disposed on and in contact with the first surface of the encapsulant (233, [0100]), the first surface of the at least one inactive element (231) and the first surface of the at least one semiconductor device (202), and a plurality of inner vias (235, [0100]), which is formed at the dielectric layer, electrically connected to the at least one semiconductor device and the at least one through via of the at least one inactive element (231).
Claims 1-13 are rejected under 35 U.S.C. 103 as being obvious over Brun et al (US 20230074181 A1) in view of LI et al (US 20250062285 A1).
Regarding claim 1, Figure 1 of Brun discloses a package structure, comprising:
at least one semiconductor device (106B, [0032]);
at least one inactive element (106A, [0032] and [0034], considering die with passive circuits only) disposed around the at least one semiconductor device, and including a main portion (upper portion of 106A in the Figure 1) and at least one through via (vertical connection line in 106A) extending through the main portion; and
an encapsulant (108, [033]) encapsulating the at least one semiconductor device (106B) and the at least one inactive element (106A).
Brun does not teach wherein a first surface of the encapsulant is substantially coplanar with a first surface of the at least one inactive element and a first surface of the at least one semiconductor device, and a second surface of the encapsulant is substantially coplanar with a second surface of the at least one inactive element and a second surface of the at least one semiconductor device; wherein the at least one semiconductor device comprises: a main portion, wherein the second surface of the at least one semiconductor device is defined at a bottom surface of the main portion, such that the bottom surface of the main portion is coplanar with the second surface of the encapsulant and the second surface of the at least one inactive element: an active circuit structure disposed on the main portion, wherein the top surface of the at least one semiconductor device is defined at a top surface of the active circuit structure, such that the top surface of the active circuit structure is coplanar with the first surface of the encapsulant and the first surface of the at least one inactive element: and at least a pad embedded in the active circuit structure from the top surface thereof, wherein the pad is exposed from the top surface of the active circuit structure, such that a top surface of the pad, the first surface of the encapsulant, and the first surface of the at least one inactive element are coplanar.
However, LI is a pertinent art which teaches a semiconductor package that use a face-to-face stacked die configuration (Figure 1) to achieve various IC design goals. In this context, a “face” of a die refers to the surface of the die adjacent to an active region of the die that includes active circuitry. For example, the active region can include various layers and structures that define circuit elements, such as transistors, conductors, passive circuit elements (e.g., resistors, inductors, capacitors, etc.). In this example, the face of the die corresponds to the side of the die that bounds this active region. In contrast, a “back” of the die refers to an opposite side of the die which bounds an inactive region of the die. For example, the inactive region typically includes undoped monocrystalline semiconductive material and other inactive layers (e.g., passivation layers) ([0020]). Further, Figures 1-4 of LI teaches a first surface of an encapsulant (170) is substantially coplanar with a first surface of the at least one inactive element (240) and a first surface of the at least one semiconductor device (130, [0038]), and a second surface of the encapsulant is substantially coplanar with a second surface of the at least one inactive element and a second surface of the at least one semiconductor device. LI further teaches that such arrangement improves performance, shorter signal path and cost ([0023]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of CHOI as claimed above according to the teaching of LI in order to improve performance and shorten signal path and lower cost ([0023] of LI).
Regarding claim 2, Figure 1 of Brun in view of LI teach that the package structure of claim 1, wherein a width of the at least one semiconductor device is greater than a width of the at least one inactive element (Figure 2 of LI teaches that a lateral width of 130 is greater than 240).
Regarding claim 3, Figure 1 of Brun discloses that the package structure of claim 1, wherein a thickness of the main portion of the at least one semiconductor device is less than a thickness of the main portion of the at least one inactive element (Figures 1-2 of LI teaches that a thickness of the main portion 136 of the at least one semiconductor device is less than a thickness of the main portion of the at least one inactive element 240).
Regarding claim 4, Figure 1 of Brun discloses that the package structure of claim 3, wherein a material of the main portion of the at least one semiconductor device (106B) is same as a material of the main portion of the at least one inactive element (106A) (based on the Figure).
Regarding claim 5, Figure 1 of Brun discloses that the package structure of claim 3, wherein the active circuit structure (106B) includes at least one pad (connections at the top surface of the die 106B) exposed from the first surface (top surface) of the at least one semiconductor device.
Regarding claim 6, Figure 1 of Brun discloses that the package structure of claim 3, wherein the at least one semiconductor device (106B) does not include a vertical conduction path in the main portion of the at least one semiconductor device (no via in 106B based on the Figure).
Regarding claim 7, Figure 1 of Brun discloses that the package structure of claim 1, wherein the at least one inactive element (106A) does not include a horizontal conduction path on the main portion of the at least one inactive element.
Regarding claim 8, Figure 1 of Brun discloses that the package structure of claim 1, wherein a first surface (top surface) of the at least one through via (vertical lines within 106A are the vias and exposed at the top surface of 106A) of the at least one inactive element is exposed from the first surface of the at least one inactive element, and a second surface (bottom surface) of the at least one through via of the at least one inactive element (vertical lines within 106A are the vias and exposed at the bottom surface of 106A) is exposed from the second surface of the at least one inactive element.
Regarding claim 9, Figure 1 of Brun discloses that the package structure of claim 1, wherein the at least one inactive element includes a first inactive element (106A, left one) and a second inactive element (106A, right one) disposed around the first semiconductor device and the second semiconductor device.
Brun does not explicitly teach wherein the at least one semiconductor device includes a first semiconductor device and a second semiconductor device disposed side by side.
However, Brun teaches that a particular number and arrangement of structures and components are presented for illustrative purposes and any desired number or arrangement of such structures and components may be present in various embodiments. Further, the structures shown in the figures may take any suitable form or shape according to material properties, fabrication processes, and operating conditions ([0027]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Brun in view of LI wherein the at least one semiconductor device includes a first semiconductor device and a second semiconductor device disposed side by side in order to increase the functionality of the package according to the teaching of Adan, since the court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 10, Figure 1 of Brun discloses that the package structure of claim 9, wherein the encapsulant (108) is disposed in a space between the first semiconductor device and the first inactive element, a space between the first semiconductor device and the second semiconductor device, and a space between the second semiconductor device and the second inactive element (Figure 1 teaches that each of the devices are separated by the encapsulant 108).
Regarding claim 11, Figure 1 of Brun discloses that the package structure of claim 1, further comprising: a redistribution structure (layer between 108 and 130) disposed on the first surface of the encapsulant (108), the first surface of the at least one inactive element (106A) and the first surface of the at least one semiconductor device (106B), and electrically connected to the at least one semiconductor device and the at least one through via of the at least one inactive element.
Regarding claim 12, Figure 1 of Brun discloses that the package structure of package structure of claim 1, further comprising: an upper electronic device (130, [0037], considering dies 102 including the molding is an electronic device on a broadest reasonable interpretation) disposed over the first surface of the encapsulant (108), the first surface of the at least one inactive element (106A) and the first surface of the at least one semiconductor device (106B), and electrically connected to the at least one semiconductor device and the at least one through via of the at least one inactive element (106A).
Regarding claim 13, Figure 1 of Brun discloses that the package structure of claim 12, wherein a lateral surface of the upper electronic device (130, [0037]) is substantially aligned with a lateral surface of the encapsulant (108).
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claim 1, filed on 08/06/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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