Prosecution Insights
Last updated: July 15, 2026
Application No. 18/600,997

PACKAGE STRUCTURE INCLUDING INACTIVE ELEMENT, ASSEMBLY STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102
Filed
Mar 11, 2024
Examiner
TRAPANESE, WILLIAM C
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
493 granted / 640 resolved
+9.0% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
26 currently pending
Career history
667
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
78.2%
+38.2% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
0.4%
-39.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102
33Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shanmugam et al. (hereinafter Karthik, US 2022/0157680). In regards to independent claim 1, Karthik teaches a package structure, comprising: a first molded structure having a first surface and a second surface opposite to the first surface (Karthik, Fig. 3E, 110), and comprising: at least one semiconductor device (Karthik, Fig. 3E, 102); at least one inactive element disposed around the at least one semiconductor device, and including a main portion and at least one through via extending through the main portion (Karthik, Fig. 3E, 142, 140); and an encapsulant encapsulating the at least one semiconductor device and the at least one inactive element (Karthik, Fig. 3E, 110); a first redistribution structure disposed on the first surface of the first molded structure (Karthik, Fig. 3E, 120); and a second redistribution structure disposed on the second surface of the first molded structure, and electrically connected to the first redistribution structure through the at least one through via of the at least one inactive element (Karthik, Fig. 6, 300). In regards to dependent claim 2, Karthik teaches wherein a first surface of the encapsulant of the first molded structure is substantially coplanar with a first surface of the at least one inactive element of the first molded structure and a first surface of the at least one semiconductor device of the first molded structure, and a second surface of the encapsulant of the first molded structure is substantially coplanar with a second surface of the at least one inactive element of the first molded structure and a second surface of the at least one semiconductor device of the first molded structure (Karthik, Fig. 3-5, 120, 110, 142, 102). In regards to dependent claim 3, Karthik teaches wherein the at least one semiconductor device of the first molded structure include a main portion and an active circuit structure disposed on the main portion, wherein a thickness of the main portion of the at least one semiconductor device of the first molded structure is less than a thickness of the main portion of the at least one inactive element of the first molded structure (Karthik, Fig. 3E, 106, 120, 142, 140). In regards to dependent claim 4, Karthik teaches wherein a material of the main portion of the at least one semiconductor device of the first molded structure is same as a material of the main portion of the at least one inactive element of the first molded structure (Karthik, Fig. 3E, 142, 102, copper). In regards to dependent claim 5, Karthik teaches wherein the active circuit structure of the at least one semiconductor device of the first molded structure includes at least one pad exposed from the first surface of the at least one semiconductor device of the first molded structure (Karthik, Fig. 3E,120, 106, 102). In regards to dependent claim 6, Karthik teaches wherein the at least one semiconductor device of the first molded structure does not include a vertical conduction path in the main portion of the at least one semiconductor device of the first molded structure (Karthik, Fig. 3E, 120,102,106). In regards to dependent claim 7, Karthik teaches wherein the at least one inactive element of the first molded structure does not include a horizontal conduction path on the main portion of the at least one inactive element of the first molded structure (Karthik, Fig. 3E, 142, 140). In regards to dependent claim 8, Karthik teaches wherein a first surface of the at least one through via of the at least one inactive element of the first molded structure is exposed from the first surface of the at least one inactive element of the first molded structure, and a second surface of the at least one through via of the at least one inactive element is exposed from the second surface of the at least one inactive element of the first molded structure (Karthik, Fig. 3E, 120, 142, 140). In regards to dependent claim 9, Karthik teaches wherein the at least one semiconductor device of the first molded structure includes a first semiconductor device and a second semiconductor device disposed side by side, and the at least one inactive element of the first molded structure includes a first inactive element and a second inactive element disposed around the first semiconductor device and the second semiconductor device (Karthik, Fig. 3E, 120, 102). In regards to dependent claim 10, Karthik teaches wherein the encapsulant of the first molded structure is disposed in a space between the first semiconductor device and the first inactive element, in a space between the first semiconductor device and the second semiconductor device, and in a space between the second semiconductor device and the second inactive element (Karthik, Fig. 3E, 102, 142). In regards to dependent claim 11, Karthik teaches the package structure of claim 1, further comprising: a second molded structure disposed under the first molded structure, and comprising: at least one semiconductor device; at least one inactive element disposed around the at least one semiconductor device, and including a main portion and at least one through via extending through the main portion; and an encapsulant encapsulating the at least one semiconductor device and the at least one inactive element; and a third redistribution structure disposed between the first molded structure and the second molded structure (Karthik, Fig. 3E, Fig. 7, 110, 142, 102). In regards to dependent claim 12, Karthik teaches the package structure of claim 11, wherein a first surface of the encapsulant of the second molded structure is substantially coplanar with a first surface of the at least one inactive element of the second molded structure and a first surface of the at least one semiconductor device of the second molded structure, and a second surface of the encapsulant of the second molded structure is substantially coplanar with a second surface of the at least one inactive element of the second molded structure and a second surface of the at least one semiconductor device of the second molded structure (Karthik, Fig. 3E, 110, 142, 102). In regards to dependent claim 13, Karthik teaches the package structure of package structure of claim 1, further comprising: an upper electronic device disposed over and electrically connected to the first redistribution structure (Karthik, Fig. 3E, 120, 400, 402). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Mar 11, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102
Jul 06, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12672332
LDMOS DEVICE AND METHOD OF FABRICATION OF SAME
3y 7m to grant Granted Jun 30, 2026
Patent 12660318
ARRAY SUBSTRATE, AND DISPLAY PANEL
3y 2m to grant Granted Jun 16, 2026
Patent 12641852
HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF, CHIP, AND ELECTRONIC DEVICE
2y 11m to grant Granted May 26, 2026
Patent 12635170
SHIELDED GATE TRANSISTOR
3y 2m to grant Granted May 19, 2026
Patent 12588341
DISPLAY PANEL AND ELECTRONIC DEVICE
2y 11m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
98%
With Interview (+20.9%)
3y 2m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month